Extended Data Table 1 Hardware structure of the memristor chip

From: Federated learning using a memristor compute-in-memory chip with in situ physical unclonable function and true random number generator

  1. a, Hardware structure of memristor chip for federated learning. The chip consists of 72 XBs and a shared SRAM. b, Hardware structure of memristor CIM XB. Each XB contains a 2048×2048 memristor array, BL and WL drivers, sample & holds, 16-1 MUX, 128 ADCs, and 128 shift & adders. BL, bit line. WL, word line. c, Basic parameters of the memristor chip.
Back to article page