Extended Data Table 3 Hardware structure and the area of the digital ASIC chip for federated learning

From: Federated learning using a memristor compute-in-memory chip with in situ physical unclonable function and true random number generator

  1. a, The hardware structure of the chip. The chip contains 4800 1-bit TRNGs, 6 MAC arrays and 4 DRAM PHYs. b, The hardware structure of the MAC array. The MAC array contains 64 parallel 4-bit multiplexers & adders, and 64 256×8bits SRAMs. c, The hardware structure of the 4-bit multiplexer & adder. d, Parameters of each module. e, The configuration and the area breakdown of the ASIC chip.
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