Fig. 5: Low-power CMOS logic circuits based on high-κ HZO dielectrics. | Nature Electronics

Fig. 5: Low-power CMOS logic circuits based on high-κ HZO dielectrics.

From: Integration of freestanding hafnium zirconium oxide membranes into two-dimensional transistors as a high-κ ferroelectric dielectric

Fig. 5: Low-power CMOS logic circuits based on high-κ HZO dielectrics.The alternative text for this image may have been generated using AI.

a, Transfer characteristics of an inverter operation at different VDD varying from 1.5 to 2 V (left). Calculated gain (|dVOUT/dVIN|) of the inverter as a function of VIN at different VDD (right). b, Noise margin characteristics of the inverter at VDD = 2 V. c, Calculated power consumption of the inverter as a function of VIN at different VDD. d–f, VOUT results and the corresponding waveforms at VDD = 2 V as functions of VIN,A and VIN,B, shown for NAND (d) and NOR (e). f, Schematic of a 1-bit full adder and the corresponding waveforms at VDD = 2 V as functions of VIN,A and VIN,B. Sum and Cout denote the sum and carry-out outputs of the 1-bit full adder, respectively, reflecting the arithmetic result and the propagated carry bit.

Back to article page