Fig. 3: Hybrid FeCAP/memristor memory circuit and array.
From: A ferroelectric–memristor memory for both training and inference
a, Array-level organization of the hybrid memories and peripheral circuit. b, Optical micrograph of the fabricated array. c, Schematic of the hybrid FeCAP/memristor memory circuit. d, To account for the significance of the MSBs during the data transfer process, the MSBs are implemented using capacitors with distinct areas: four times the minimum area, twice the minimum area and minimum area, respectively, for the first, second and third MSBs. e, Average voltage measurements after loading the transfer line (TL), and reading a zero or a one as a function of the capacitor area, with standard deviation at 1σ.
