Abstract
Scalable superconducting memory is required for the development of low-energy superconducting computers and fault-tolerant quantum computers. Conventional superconducting logic-based memory cells possess a large footprint that limits scaling; nanowire-based superconducting memory cells, although more compact, have high error rates, which hinders integration into large arrays. Here we report a 4 × 4 superconducting nanowire memory array that is designed for scalable row–column operations and has a functional density of 2.6 Mbit cm−2. Each memory cell is based on a nanowire loop consisting of two temperature-dependent superconducting switches and a variable kinetic inductor. The arrays operate at 1.3 K, where we implement and characterize multiflux quanta state storage and destructive read-out. By optimizing the write- and read-pulse sequences, we minimize bit errors and maximize operating margins. We achieve a minimum bit error rate of 10−5. We also use circuit-level simulations to understand the memory cell’s dynamics, performance limits and stability under varying pulse amplitudes.
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Data availability
The data that support the findings of this study are available from the corresponding authors upon reasonable request.
Code availability
The code used for the simulations and data analysis in this study is available from the corresponding authors upon reasonable request.
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Acknowledgements
We thank E. Golden and P. D. Keathley for their review during the preparation of this manuscript. This work was funded by the DOE, Office of Science Research Program for Microelectronics Codesign, through the project ‘Hybrid Cryogenic Detector Architectures for Sensing and Edge Computing Enabled by New Fabrication Processes’ (LAB 212491). Fabrication was carried out in part through the use of MIT.nano’s facilities, with technical guidance from J. Daley and M. Mondol. Initial fabrication development was funded through the Breakthrough Starshot Foundation. O.M. acknowledges support through the National Defense Science and Engineering Graduate (NDSEG) Fellowship Program. A.S. acknowledges NSF GRFP and MIT Vanu Bose Presidential fellowships. R.F. acknowledges the Alan McWhorter Fellowship.
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O.M., M. Castellani, B.B., M. Colangelo and K.K.B. conceived and designed the experiments. M. Castellani and O.M. performed the experiments. O.M., M. Castellani, V.K., R.F., A.S., F.I., M. Colangelo and K.K.B. analysed the data. V.K., R.F., A.S., F.I. and B.B. contributed materials and analysis tools. All authors contributed to the writing of the paper.
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Nature Electronics thanks Vladimir Krasnov, Cezar Zota and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.
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Medeiros, O., Castellani, M., Karam, V. et al. A scalable superconducting nanowire memory array with row–column addressing. Nat Electron 9, 69–77 (2026). https://doi.org/10.1038/s41928-025-01512-0
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DOI: https://doi.org/10.1038/s41928-025-01512-0
