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The design of analogue in-memory computing tiles

Nature Electronics volume 8, pages 1156–1169 (2025)Cite this article

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Abstract

Analogue in-memory computing (AIMC) is an emerging computational approach that executes operations directly within memory arrays, reducing the need for data transfer between memory and processing units. AIMC-based accelerators are, in particular, being explored for deep neural network (DNN) inference, with the key element of such accelerators being the AIMC tile, which can be implemented using various conventional volatile charge-based and emerging non-volatile resistive memory (memristive) technologies. Here we examine the design of non-volatile memristive AIMC tiles for DNN accelerators. We explore the different components of a memristive AIMC tile and the range of mapping techniques for encoding signed multibit weights and inputs. We provide an analysis of the efficiency and accuracy of output encoding schemes, including various analogue-to-digital converter approaches. We also provide a comparative analysis of the different memory technologies being explored and projections for how technology scaling may impact key design components.

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Fig. 1: IMC-based AI accelerator.
Fig. 2: IMC tile.
Fig. 3: Detailed overview of an AIMC tile.
Fig. 4: Output encoding block and ADC types.
Fig. 5: Comparative study of prominent IMC tiles.
Fig. 6: Recent trends and technological projections.

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Data availability

The data that support the plots within this paper are available from the corresponding authors upon reasonable request.

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Acknowledgements

We thank P. A. Francese, S. Tsai, V. Narayanan and J. Burns for technical discussions and management support.

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Authors and Affiliations

  1. IBM Research Europe, Rüschlikon, Switzerland

    Abhairaj Singh, Manuel Le Gallo, Athanasios Vasilopoulos & Abu Sebastian

  2. IBM Research—Almaden, San Jose, CA, USA

    Jose Luquin, Pritish Narayanan & Geoffrey W. Burr

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  1. Abhairaj Singh
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A. Singh, M.L.G. and A. Sebastian conceived of the overall research idea and coordinated the project. The manuscript was initially drafted by A. Singh, with substantial input through comments, revisions and structural guidance from A.V., M.L.G. and A. Sebastian. J.L., P.N. and G.W.B. provided critical reviews focused on the technical content and paper structure. P.N. contributed specifically to refining and streamlining the technical content, while G.W.B. offered detailed feedback on the overall presentation of the key contributions, especially in the Introduction and figures. All authors reviewed the final paper and contributed to its revision and approval.

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Correspondence to Abhairaj Singh or Abu Sebastian.

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Singh, A., Le Gallo, M., Vasilopoulos, A. et al. The design of analogue in-memory computing tiles. Nat Electron 8, 1156–1169 (2025). https://doi.org/10.1038/s41928-025-01537-5

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