Fig. 1
From: Negative capacitance from the inductance of ferroelectric switching
Negative-capacitance Si junctionless transistor (NC-JLT) and the gate stack. a The schematic of the transistor and the layer structure of the gate stack. b, c are the cross-sectional transmission electron microscope (TEM) and scanning electron microscope (SEM) images of the Si channel and the gate stack. d Ferroelectric characteristics of the as-deposited zirconium oxide (ZrO2) metal–ferroelectric–metal (MFM) structure, exhibiting significant polarization–electric field (P–E) hysteresis loop and switching current. The inset shows the schematic diagram of the as-deposited ZrO2 MFM structure. e, f Electrical characteristics of the NC-JLT. e The forward and backward Id–Vgs curves at Vds = 0.05 and 1 V, respectively, indicating the hysteresis-free Id–Vgs characteristics. f The subthreshold swing (SS) as a function of Vgs at a large drain voltage of Vds = 1V, revealing sub-60 mV/dec SS with a minimum value of 46mV/dec
