Fig. 2: Scanning tunneling microscope (STM)-patterned single electron transistors (SETs).
From: Atomic-scale control of tunneling in donor-based devices
a Electrical contacts (sketched in white) overlaid on top of an STM-patterned SET device. b STM image of the central device region of a typical SET device acquired immediately following hydrogen lithography. The central device region shows a central island that is tunnel coupled with source and drain leads and capacitively coupled to two in-plane gates. Gate 2 is patterned with a deliberate shift towards the source electrode to allow tuning the tunnel coupling symmetry. A high-resolution STM image at the center region is overlaid on a large-scale lower-resolution STM image. c Atomic resolution STM image of an SET pattern where the tunnel gaps are defined with atomic precision. The imaged rows running from upper left to lower right are 2 × 1 surface reconstruction dimer rows on the Si(100) surface. The junction gap separation, d, and junction width, w, are marked in the image. The circle marks the image of a single dangling bond. The STM image is taken at −2 V sample bias and 0.1 nA setpoint current. d An equivalent circuit diagram for the SET, where tunnel junctions are treated as a tunneling resistance and capacitance connected in parallel and the combined coupling of the two gates to the SET island is treated as a capacitor. Gate voltage VGS is applied to both gates in parallel with respect to the grounded source. The drain–source bias VDS is applied to the drain contact lead with respect to the grounded source. e The energy diagram of an SET, where μS and μD are the chemical potentials of the source and drain leads respectively; μIS(N) is the chemical potential of the island that is occupied with N excess electrons. EBarr is 7.
