Fig. 1: Schematics of the one-transistor design for implementing logic gates. | Communications Materials

Fig. 1: Schematics of the one-transistor design for implementing logic gates.

From: Multi-functional multi-gate one-transistor process-in-memory electronics with foundry processing and footprint reduction

Fig. 1

a Logic NOT gates comparing the conventional CMOS design (left) and the one-transistor design (right; TG: top gate). b Cross-section SEM view of the device fabricated using the Si-based SOI 130 nm technology node (scale bar: 500 nm). c One-transistor logic AND/OR gate in comparison to the six-transistor logic gates. The first input, Input1, is the voltage on the top gate, VGS, and the voltage on the side gate (SG), VSG, is the second input, Input2. The voltage on the drain electrode is VDS, and the channel current is IDS. The additional electrode connected directly to the channel represents the output of the logic gates and is the control gate of the memory. The voltage measured from the output is denoted as Output, and the voltage applied on the control gate is VCG22.

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