Fig. 2: One-transistor logic NOT gate structure, mechanism and simulation of the one-transistor design. | Communications Materials

Fig. 2: One-transistor logic NOT gate structure, mechanism and simulation of the one-transistor design.

From: Multi-functional multi-gate one-transistor process-in-memory electronics with foundry processing and footprint reduction

Fig. 2

Please kindly note that the simulation results are used to describe the mechanisms qualitatively and the two input gates functions and effects are considered to be the same to those of the one input gate. a Measured input gate voltage vs. output voltage. VDS = 0.9 V. b Mechanism comparison of logic NOT for both the MGT structure and the conventional CMOS (complementary Metal Oxide Semiconductor transistors) structure. c–f Simulation results of voltage distribution in the one-transistor design. c, e The input gate voltages turn the channel off, and the gate-to-drain voltage enables the high voltage region on the drain edge to extend from the drain to the output for logic NOT and logic NAND, respectively. d, f The input gate voltage turns the channel on so that the output voltage is drawn down by the source voltage, for logic NOT and logic NAND, respectively.

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