Extended Data Fig. 7: Simplified chip circuit overview.
From: Real-time raw signal genomic analysis using fully integrated memristor hardware
Only four rows and columns are shown here, while the actual chip implements a 64 x 64 array. The chip integrates MUXs, TIAs, S&H, and ADCs. Each column is equipped with a TIA and S&H module, while every 16 columns share one ADC. The row MUX can select between Float, Vpulse, Vref, Vread, and GND; while the column MUX can choose among Float, Vpulse, Vref, GND, and a connection to TIA. When input data arrives, the scan chain sequentially loads the input data into row and column latches. These latches then feed the addresses to the row and column MUXs to enable proper array access.
