The FAMES pilot line on fully depleted silicon-on-insulator technology provides a complete toolbox of technologies for the development of innovative chip architectures with increased performance and lower power consumption of mixed-signal circuits.
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Acknowledgements
We thank the following people from CEA-Leti who helped with proposal preparation: T. Poiroux, Y. Bogumilowicz, M. Charbonneau, E. Petitprez, T. Ernst, R. Segaud, F. Andrieu, A. Cognault-Branly, E. Mercier, P. Batude, E. Ollier, P. Vincent, L. Pain, C. Ogier-Falzon. In addition, we thank the following FAMES partners: M. Moridi, P. Pursula, G. Fagas, J. de Boeck, C. Kutter, V. Kilchytska, F. Gamiz, R. Beck, P. Caulier and L. Fesquet.
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Related links
ECSEL: https://www.ecsel-portal.eu
ENIAC: https://www.eniac.vc/
EU Green Deal: https://commission.europa.eu/strategy-and-policy/priorities-2019-2024/european-green-deal_en
European Chips Act: https://commission.europa.eu/strategy-and-policy/priorities-2019-2024/europe-fit-digital-age/european-chips-act_en
FAMES: https://fames-pilot-line.eu
Key Digital Technologies: https://eu-careers.europa.eu/en/kdt-key-digital-technologies-joint-undertaking
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Lèquepeys, JR., Noguet, D., Paing, B. et al. Europe’s pilot line on fully depleted silicon-on-insulator technology (FAMES). Nat Rev Electr Eng 2, 77–78 (2025). https://doi.org/10.1038/s44287-025-00144-y
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DOI: https://doi.org/10.1038/s44287-025-00144-y
