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Thermal management materials for 3D-stacked integrated circuits

Nature Reviews Electrical Engineering volume 2, pages 598–613 (2025)Cite this article

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Abstract

As transistor scaling approaches nanometre and even atomic scales, 3D stacking has become a critical enabler for advancement in the semiconductor industry, especially in high-performance computing and artificial intelligence (AI) applications. However, 3D integration introduces substantial thermal management challenges related to the increased power density and constrained heat dissipation pathways, particularly through low thermal conductivity interlayer dielectrics and complex interfaces. In this Review, we discuss state-of-the-art thermal management materials, covering their process compatibility, the critical integration challenges and the need for improved methods to enhance heat transport across interfaces. Advanced thermal characterization metrologies are introduced to highlight the need for non-destructive in-line metrologies. Finally, we provide a road map that outlines future research directions for material growth, integration and characterization methodologies to enable viable thermal solutions for 3D integration and beyond.

Key points

  • The shrinking dimensions, increased structural complexity and 3D stacking of silicon-based semiconductor devices are intensifying challenges in thermal dissipation.

  • Breakthroughs are needed to address maximum temperatures near hot spots in 3D-stacked devices, requiring innovation in material growth, processing and integration.

  • Advancements are necessary in the characterization of the thermal properties of the materials and in the methods to enhance heat transport across interfaces.

  • The development of non-destructive in-line metrologies compatible with semiconductor processing flows is highly desirable for the characterization of thermal management film stacks and the monitoring of thermal dissipation performance within chips.

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Fig. 1: Device architecture and system integration induced thermal dissipation issues.
Fig. 2: Integration challenges of thermal management materials.
Fig. 3: Working principle of the 3ω method.
Fig. 4: Capabilities of thermal characterization techniques.

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Authors and Affiliations

  1. Pathfinding, Research and Development, Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan

    W.-Y. Woon, J.-R. Wen, K. K. Hu, J.-H. Jhang, C. C. Shih, J. F. Hsu & S. Sandy Liao

  2. Electrical Engineering, Stanford University, Stanford, CA, USA

    A. Kasperovich, M. Malakoutian & S. Chowdhury

  3. Corporate Research, Research and Development, Taiwan Semiconductor Manufacturing Company, San Jose, CA, USA

    S. Vaziri, I. Datye & X. Y. Bao

  4. Institute of Industrial Science, The University of Tokyo, Tokyo, Japan

    Y. Wu & M. Nomura

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W.-Y.W., A.K., J.-R.W., K.K.H., M.M., J.-H.J., S.V., I.D., C.C.S., J.F.H. and Y.W. researched data for the article. W.-Y.W., A.K., J.-R.W., K.K.H., M.M., J.-H.J., S.V., I.D., C.C.S., J.F.H., M.N. and S.S.L. substantially contributed to the discussion of the content. W.-Y.W., A.K., J.-R.W., K.K.H., S.V., J.F.H., M.N. and S.S.L. wrote the manuscript. W.-Y.W., X.-Y. B., S.C. and S.S.L. reviewed and edited the manuscript before submission.

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Woon, WY., Kasperovich, A., Wen, JR. et al. Thermal management materials for 3D-stacked integrated circuits. Nat Rev Electr Eng 2, 598–613 (2025). https://doi.org/10.1038/s44287-025-00196-0

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