The endurance, retention and system-level performance of memristors for memory and computation has been often misrepresented in articles that lack statistics and use non-standardized characterization and simulation protocols. Here we discuss the origin of these issues, their negative effect in the nascent memristor industry, and potential ways to mitigate them.
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References
Gelman, A. & Stern, H. The difference between “significant” and “not significant” is not itself statistically significant. Am. Stat. 60, 328–331 (2006).
Lanza, M. et al. Standards for the characterization of endurance in resistive switching devices. ACS Nano 15, 17214–17231 (2021).
Aguirre, F. et al. Hardware implementation of memristor-based artificial neural networks. Nat. Commun. 15, 1974 (2024).
Lanza, M. et al. The gap between academia and industry in resistive switching research. Nat. Electron. 6, 260–263 (2023).
Lanza, M. et al. Recommended methods to study resistive switching devices. Adv. Electron. Mater. 1800143 (2018).
Lanza, M. et al. Memristive technologies for data storage, computation, encryption, and radio-frequency communication. Science 376, eabj9979 (2022).
Chen, A. Forming voltage scaling of resistive switching memories. 71st Device Research Conference 181–182 (2013).
Fukuyama, S. et al. Comprehensive analysis of data-retention and endurance trade-off of 40nm TaOx-based ReRAM. In 2019 IEEE International Reliability Physics Symposium (IRPS) https://doi.org/10.1109/IRPS.2019.8720436 (2019).
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F.A. is an employee of Intrinsic Semiconductor, which is seeking to commercialize memristors.
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Lanza, M., Pazos, S. & Aguirre, F. The Achilles’ heel of memristive technologies. Nat Rev Electr Eng 2, 654–656 (2025). https://doi.org/10.1038/s44287-025-00207-0
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DOI: https://doi.org/10.1038/s44287-025-00207-0
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