Abstract
As semiconductor-based electronic technologies continue downscaling, there is an urgent need to overcome the limitations of interconnect architectures and materials that are driving an unsustainable increase in energy consumption and jeopardizing performance. In this Review, we investigate the primary causes of prolonged signal delays in interconnect systems, providing an overview of the development of key interconnect components: metals, diffusion barriers and intermetal dielectrics. We define the essential requirements and technological hurdles for next-generation materials to be industrialized within damascene processes, including topological semi-metals such as molybdenum phosphide (MoP) and 2D materials such as graphene and amorphous boron nitride (a-BN). Integrating new materials into advanced device systems offers opportunities for the advancement of interconnect technologies and highly integrated semiconductor devices.
Key points
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As semiconductor devices relentlessly scale down, mitigating critical signal delay in interconnects requires cutting-edge materials with a low metal resistance, robust thin diffusion barrier and low intermetal dielectric (IMD) capacitance.
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Topological semi-metals such as molybdenum phosphide (MoP) and MoTe2 for metals, 2D materials such as graphene and MoS2 for diffusion barriers, and transformed 2D materials such as amorphous boron nitride (a-BN) for IMDs hold immense potential to surpass these constraints.
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The successful industrialization of these novel materials requires breakthroughs in the basic science to achieve ideal properties and engineering solutions to ensure seamless integration with current damascene processes.
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The discovery of novel materials, coupled with advances in process engineering, will create interconnect technologies that offer more efficient and sustainable performance.
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Acknowledgements
H.-J.S. acknowledges support from the National Research Foundation of Korea (NRF) grant funded by the Korean Government Ministry of Science and ICT (MSIT) (grant no. RS-2024-00352458), the GIST research fund (Future-leading Specialized Research Project, 2025) and the InnoCORE programme of the MSIT (GIST InnoCORE KH0830). H.S.S acknowledges support from the Institute for Basic Science (IBS-R036-D1), Republic of Korea. M.C. acknowledges support from the European Research Council (ERC) Advanced Grant (grant agreement GA 101019828-2D-LOTTO) and EPSRC (EP/ T026200/1, EP/T001038/1). J.J.C. acknowledges support from the US National Science Foundation Division of Materials Research (FUSE 2328907). O.K. acknowledges REDI Program funding and a Marie Skłodowska-Curie Grant (no. 101034328). S.R. acknowledges 2021 SGR 00997, CERCA Programme of the Generalitat de Catalunya, Severo Ochoa Centres of Excellence Programme (grant no. CEX2021-001214-S) and MCIN/AEI/10.13039.501100011033.
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H.-J.S. conceptualized this work. H.K., S.O., S.A. and H.-J.S. researched data for the article and wrote the manuscript. J.K., T.K. J.J.C., M.C. and H.S.S. contributed substantially to discussion of the content, and reviewed and edited the manuscript. S.J., O.K., T.G. and S.R. reviewed and edited the manuscript. J.J.C., M.C., H.S.S. and H.-J.S. supervised this project.
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Kim, H., Oh, S., An, S. et al. Future interconnect materials for highly integrated semiconductor devices. Nat Rev Electr Eng 2, 835–845 (2025). https://doi.org/10.1038/s44287-025-00233-y
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