Fig. 7: CMOS+ X (stochastic MTJ) platforms.
From: Connecting physics to systems with modular spin-circuits
a An sMTJ-based binary stochastic neuron (p-bit) is interfaced with a digital CMOS-based circuit to trigger a digital p-bit emulator. The bottom panel shows SPICE results for the analog fluctuations at the drain (VsMTJ) of the NMOS transistor. b Rail-to-rail stochastic fluctuations are obtained after a buffer tree (VINTER) is inserted between the single sMTJ-based p-bit and the large digital CMOS block. CMOS block contains a low-quality and inexpensive pseudo-random number generator (PRNG) along with a look-up table to obtain tunability. This hybrid setup with the sMTJ circuit increases the quality of randomness that can be obtained from the digital p-bit block alone (see ref. 65). c Tunability of the heterogeneous structure as a probabilistic bit is shown with time-averaged VOUT over 1000 ns in SPICE. d In the future, millions of sMTJs can provide nearly-free true randomness to CMOS underlayers for various probabilistic computing applications.
