Fig. 4: Computing with steady digital states.

Only one direction of magnetization vector is taken as an order parameter. a A full adder constructed from NOT and NAND gates. b Schematic of current-driven domain wall inverter using chirally coupled domains through a chiral domain wall. c Magnetic force microscopy image of the full adder logic operation, A (0) + B (1) = Sum (1) + Cout (0). The current-driven domain wall motion is used to construct full adders. d A majority logic gate constructed from NAND gates. e Schematic of majority logic gate constructed from magneto-electric spin-orbit (MESO) logic. f Input-output transfer curve in MESO logic. The magnetoelectric spin-orbit devices can implement majority gates. Parts (b, c) reprinted with permission from ref. ³⁸, Springer Nature Limited. Part (f) reprinted with permission from ref. ³⁶, Springer Nature Limited.