Fig. 3: The hardware implementation of the hash layer.
From: In-memory search with learning to hash based on resistive memory for recommendation acceleration
a Schematic of VMM operations for hash code generation. Here, bipolar weights are stored in the RRAM array as different resistance state combinations, represented by pairs of adjacent RRAM cells. b The truth table of a single RRAM cell is provided for clarity. c The readout resistance map, which represents different MAC situations, is displayed after a 9 × 8 binary weight matrix is stored in the crossbar. d The voltage distributions of corresponding MAC results. The final hash codes can be obtained through a sense amplifier (SA).
