Fig. 1: Implementation of single-phase in-memory MVM.
From: Demonstration of 4-quadrant analog in-memory matrix multiplication in a single modulation
a In-memory MVM in four phases. Inputs of positive and negative polarity are applied individually to weights of positive and negative polarity using a single voltage polarity (V−) in four modulation cycles 4TPWM. b In-memory MVM in a single phase. Inputs of positive and negative polarity are applied simultaneously to weights of positive and negative polarity with voltages of opposite polarity (V+, V−) in one modulation cycle TPWM. c Implementation of the single-phase in-memory MVM on the IBM HERMES Project Chip. The procedure is shown for a single BL of an AIMC core of the chip. ΔV refers to the voltage drop on the SL with respect to Vcm, e.g., ΔV = V+,− − Vcm. In the abbreviations for the SL connections shown on the left, the first letter refers to the SL polarity, and the second to the polarity of the read voltage applied at the bottom electrode of the PCM devices. For example, PN means connecting SLP to V−. When the SL input is >0, the PN and NP switches are activated, and when it is <0, PP and NN are activated.
