Fig. 4: Temporal logic. | npj Unconventional Computing

Fig. 4: Temporal logic.

From: Hyper flexible neural networks rapidly switch between logic operations in a compact four neuron circuit

Fig. 4

A Protocol for the temporal logic gate. The difference between the timing of the square pulses determines the symbols (1, 1), (1, 0), (0, 1), and (0, 0). The difference in timing is 10 ms. The difference between signals is exaggerated for clarity. The Truth tables for NXOR, NIMP, NAND and XOR are shown. B The LIF version of an NXOR gate. The activity of the excitatory neurons (E1 & E2) and the output neuron (Out) are shown. A cartoon representation of the input protocol is shown. C The LIF version of a NAND gate. The activity of the excitatory neurons and the output neuron are shown. D The LIF version of the NIMP gate. This gate is the logical negation of the Imply gate. E The LIF version of the XOR gate.

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