Fig. 6: Phase logic. | npj Unconventional Computing

Fig. 6: Phase logic.

From: Hyper flexible neural networks rapidly switch between logic operations in a compact four neuron circuit

Fig. 6

A Protocol for the phase logic gate. The difference between the phase of the sine waves determines the input state, i.e., (1, 1) synchrony, (1, 0) phased advanced, (0, 1) phase delayed, and (0, 0) anti-synchronized. The truth tables for NIMP delayed, and NIMP advanced are shown. B The IZH version of a NIMP delayed gate. The activity of the output neuron is shown. A cartoon representation of the input protocol is shown. C The IZH version of a NIMP advanced gate. The activity of the excitatory neurons and the output neuron are shown.

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