Fig. 5: Detailed circuit diagram of the 48×128 DCIM array. | npj Unconventional Computing

Fig. 5: Detailed circuit diagram of the 48×128 DCIM array.

From: A compact digital compute-in-memory Ising annealer with probabilistic SRAM bit in 28 nm for travelling salesman problem

Fig. 5: Detailed circuit diagram of the 48×128 DCIM array.

All MSB and LSB are grouped together, allowing easier control of noise application to specific bits via VDDM. Each cell TG signal is shared across 8 rows within the same cluster block. The spin IN signal, generated based on the spin states, is shared across 48 columns. The DCIM bitcell consists of a 6T SRAM bitcell, a 4T NOR gate and a 2T TG.

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