Figure 1 | Scientific Reports

Figure 1

From: Polarity control in WSe2 double-gate transistors

Figure 1

WSe2 flake properties and device fabrication.

(a) AFM topography image of the exfoliated flake after cleaning of tape residues with hot (50 °C) acetone bath. The red line indicated the cutline used to extract the flake thickness. (b) Height profile for the cutline showed in a. The extracted flake thickness is 7.5 nm, which corresponds to ~10 monolayers. (c) Optical image of the realized device. The channel length, including all gated regions, is 1.5 μm long of which 1 μm is gated by the bulk-Si (acting as the CG) and two 0.25 μm regions, near the contacts, are controlled by the buried program gate (horizontal parallel metal lines marked as PG). The red dotted line indicated the cutline used to represent the device schematic. (d) 3D-schematic cross-section of the device along the red cutline in (c).

Back to article page