Search

Vertical transistors based on 2D semiconductors have the potential to reduce the footprint of electronic circuits, but their high-density integration remains challenging. Here, the authors report a vertical lamination approach for realizing high-density MoS₂ vertical sidewall transistors.

The simultaneous scaling down of the channel length and gate length of 2D transistors remains challenging. Here, the authors report a self-alignment process to fabricate vertical MoS₂ transistors with sub-1 nm gate length and sub−50 nm channel length, exhibiting on-off ratios over 10⁵ and on-state currents of 250 μA/μm at 4 V bias.

Molybdenum disulfide vertical transistors with channel lengths down to one atomic layer can be made with metal electrodes using a mechanical van der Waals transfer process that leads to a high-quality metal–semiconductor interface.

Vanadium diselenide van der Waals contacts made with a controlled crack formation process can be used to fabricate tungsten diselenide transistors with channel lengths of less than 100 nm, on-state current densities of up to 1.7 mA μm^–1 and on-state resistances down to 0.50 kΩ μm.

Vertical field-effect transistors (VFETs) have potential for the realization of ultra-scaled devices, but their fabrication is usually limited by trade-offs between scalability and channel length. Here, the authors report a large-scale transfer method to realize indium gallium zinc oxide/graphene VFETs with van der Waals metallic contacts and reduced channel length.

We develop a low-temperature, damage-free process using van der Waals lamination to integrate multiple circuit tiers into a monolithic three-dimensional device, incorporating unique multi-tier functionality and resolving legacy issues with the layering technology.

Through layer-by-layer mechanical peeling, the channel region of a multilayer black phosphorus transistor can be reduced to a monolayer thickness without degrading its lattice and while retaining a multilayer contact region.

Laminated van der Waals (vdW) metallic electrodes can improve the contact of 2D electronic devices, but their scalability is usually limited by the transfer process. Here, the authors report a strategy to deposit vdW contacts onto various 2D and 3D semiconductors at the wafer scale.

The integration of high-κ dielectric layers with 2D semiconductors is essential for electronic applications, but remains challenging. Here the authors report a dry transfer method of wafer-scale Al2O3 and HfO2 thin films for the realization of top-gated monolayer MoS2 transistors and logic gates.

Here, the authors report a method to fabricate reconfigurable electronic devices based on 2D materials by using polyvinyl alcohol as substrate. This technique enables repeatable disassembling and reassembling of van der Waals heterostructures with different functionalities.

Strain engineering is a promising method to manipulate properties of two-dimensional (2D) materials but slippage between material and substrate makes strain transfer inefficient. Here the authors overcome slipping effects by encapsulating a 2D material in a polymer substrate.

Designing high-performance photodetectors based on hybrid perovskites remains a challenge. Here, the authors demonstrate that Al2O3/2D perovskite heterostructure can be utilized as photoactive dielectric for high-performance MoS2 phototransistors with broadband photoresponse, high photogain and reliability operation.

One of the challenges hindering the control of 2D transistor polarity is the incompatibility with conventional ion-implantation doping approaches. Here, the authors report a doping-free strategy to obtain polarity control of WSe₂ transistors using same-metal contacts with different integration methods.