Abstract
The Boolean satisfiability (SAT) problem is a computationally challenging decision problem central to many industrial applications. For SAT problems in cryptanalysis, circuit design, and telecommunication, solutions can often be found more efficiently by representing them with a combination of exclusive OR (XOR) and conjunctive normal form (CNF) clauses. We propose a hardware accelerator architecture that natively embeds and solves such hybrid XOR–CNF problems using in-memory computing hardware. To achieve this, we introduce an algorithm and demonstrate, both experimentally and through simulations, how it can be efficiently implemented with memristor crossbar arrays. Compared to the conventional approaches that translate XOR–CNF problems to pure CNF problems, our simulations show that the accelerator improves computation speed, energy efficiency, and chip area utilization of in-memory accelerators by ~ 10 × for a set of hard cryptographic benchmarking problems. Moreover, the accelerator achieves a ~ 10 × speedup and a ~ 1000 × gain in energy efficiency over state-of-the-art SAT solvers running on CPUs.
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Data availability
The benchmarking instances used in this study are available in ref. 57.
Code availability
The simulator used for the heuristic simulation and energy modeling is open-sourced and available at https://github.com/HewlettPackard/CountryCrab.
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Acknowledgements
The authors thank our editor, Marko Bucyk, for his careful review and editing of the manuscript, and Dmitri Strukov for discussions on XOR hardware architectures. This material is based upon work supported by the Defense Advanced Research Projects Agency (DARPA) through Air Force Research Laboratory Agreement No. FA8650-23-3-7313. The views, opinions, and/or findings expressed are those of the author(s) and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.
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H.I. and F.B. contributed equally to this work and are recognized co-first authors. H.I. and F.B. wrote the manuscript. H.I., N.K., and T.B. performed algorithm designs. M.N. and E.V. analyzed the numeric results. H.I., X.Z., and C.-W.Y. conducted the corresponding numeric benchmarking simulation. A.H. performed circuit and architectural simulations. X.S., J.I., and J.P.S. contributed to the memristor fabrication and experimental system development. G.P. and T.V.V. conceived the idea of asserting XOR clauses with in-memory computing. F.B. derived the hardware architecture, conducted the hardware modeling and energy simulations, and performed the hardware experiments. I.R. conceived the main idea of the XOR–CNF use case. I.R., T.V.V., J.P.S., M.M., and R.B. supervised and led the collaboration effort. All authors analyzed and discussed the results.
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Im, H., Böhm, F., Pedretti, G. et al. Accelerating hybrid XOR–CNF Boolean satisfiability problems natively with in-memory computing. Nat Commun (2026). https://doi.org/10.1038/s41467-026-69465-2
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DOI: https://doi.org/10.1038/s41467-026-69465-2
