Extended Data Fig. 2: Chip layout and CMOS-compatible fabrication. | Nature Photonics

Extended Data Fig. 2: Chip layout and CMOS-compatible fabrication.

From: Diffractive tensorized unit for million-TOPS general-purpose computing

Extended Data Fig. 2

a, Designed chip with commercially available processes (including 29 layout layers). b, Layout of the CMOS-compatible chip on the SOI platform. c, Passive process layers, including the designs of optical devices, and d, active process layers, including the designs of electrical devices, with the fabricated chip partially characterized by optical photos.

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