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Diffractive tensorized unit for million-TOPS general-purpose computing

Nature Photonics volume 19, pages 1078–1087 (2025)Cite this article

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Abstract

Photonic computing has emerged as a promising next-generation technology for processors, with diffraction-based architectures showing particular potential for large-scale parallel processing. Unfortunately, the lack of on-chip reconfigurability poses significant obstacles to realizing general-purpose computing, restricting the adaptability of these architectures to diverse advanced applications. Here we propose a diffractive tensorized unit (DTU), which is a fully reconfigurable photonic processor supporting million-TOPS general-purpose computing. The DTU leverages a tensor factorization approach to perform complex matrix multiplication through clustered diffractive tensor cores, while each diffractive tensor core employs a near-core modulation mechanism to activate dynamic temporal diffractive connections. Experiments confirm that the DTU overcomes the long-standing generality and scalability constraints of diffractive computing, realizing general computing with a 10−6 mean absolute error for arbitrary 1,024-size matrix multiplications. Compared with state-of-the-art solutions, the DTU not only achieves competitive accuracy on various challenging tasks, such as natural language generation and cross-modal recognition, but also delivers a 1,000× improvement in computing throughput over conventional electronic processors. The proposed DTU represents a leap forward in general-purpose photonic computing, paving the way for further advancements in large-scale artificial intelligence.

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Fig. 1: DTU consisting of dynamic DTCs for million-TOPS general-purpose computing.
Fig. 2: Systemic construction and evaluation of DTU networks.
Fig. 3: Large-scale DTU implementation of NLG.
Fig. 4: Large-scale DTU implementation of cross-modal recognition.
Fig. 5: Experimental on-chip validation of the DTU for flexible AI applications.

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Data availability

All data required to evaluate the conclusions of this study are presented in the Article or its Supplementary Information. The data repository is further available via Dryad at https://doi.org/10.5061/dryad.7d7wm387c (ref. 67). The DTU testing sample can be provided upon signing a material transfer agreement.

Code availability

All relevant code is available from the corresponding author upon reasonable request.

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Acknowledgements

This work is supported in part by National Science and Technology Major Project (contract no. 2021ZD0109903), in part by Natural Science Foundation of China (NSFC) (contract nos. 62125106, 62407026 and 62205176), in part by the Beijing Outstanding Young Scientist Program (contract no. JWZQ20240101009), in part by the XPLORER PRIZE.

Author information

Author notes

  1. These authors contributed equally: Chao Wang, Yuan Cheng, Zhihao Xu.

Authors and Affiliations

  1. Beijing National Research Center for Information Science and Technology, Department of Electronic Engineering, Tsinghua University, Beijing, China

    Chao Wang, Yuan Cheng, Zhihao Xu, Qionghai Dai & Lu Fang

  2. Department of Automation, Tsinghua University, Beijing, China

    Qionghai Dai

  3. Institute for Brain and Cognitive Science, Tsinghua University, Beijing, China

    Qionghai Dai & Lu Fang

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  1. Chao Wang
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Contributions

L.F. initiated the project, L.F. and Q.D. supervised the project, L.F. and C.W. conceived the idea, C.W. designed the photonic integrated circuit, Y.C. performed the simulations, Z.X. C.W. and Y.C. constructed the experimental system and conducted the on-chip task validations. All the authors analysed the results. C.W., Y.C., Z.X. and L.F. prepared the manuscript with input from all the authors.

Corresponding authors

Correspondence to Qionghai Dai or Lu Fang.

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The authors declare no competing interests.

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Nature Photonics thanks Shengxi Huang and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Extended data

Extended Data Fig. 1 Modeling analysis and physical architecture of a DTC.

a, Schematic structure and b, mathematical expression of on-chip modulation technologies. c, Physical architecture of the proposed DTC, with the analysis in the inset representing two classical applications of optical devices, as preliminarily validated by the numerical simulations in d and e.

Extended Data Fig. 2 Chip layout and CMOS-compatible fabrication.

a, Designed chip with commercially available processes (including 29 layout layers). b, Layout of the CMOS-compatible chip on the SOI platform. c, Passive process layers, including the designs of optical devices, and d, active process layers, including the designs of electrical devices, with the fabricated chip partially characterized by optical photos.

Extended Data Fig. 3 Integrated optoelectronic chip testing platform.

a, Constructed multifunctional experimental platform, which supports both calibration and validation of the chip. b, Example collection of the infrared spots from the OMA through the spy GCs. c, Example collection of the converted volts from the PDA obtained through the signal collector. d, Developed software for setup integration and chip testing. e, Key parts of the highly integrated experimental setup. (T-laser, tunable laser. EDFA, erbium-doped fiber amplifier. OPC, optical polarization controller. FA, fiber array. EC, edge coupler. OSP, optical splitter. GCA, grating coupler array. OMA, optical modulator array. DONN, diffractive optical neural network. PDA, photon detector array. PIC, photonic integrated circuit. NIR, near-infrared spectroscopy. IVC, current‒voltage converter. TIA, transimpedance amplifier. MVS, multichannel voltage signal source).

Extended Data Fig. 4 Detailed computational framework of benchmark models with the best settings for the DTU.

Computing network structures for various applications involving the applied a, word prediction, b, image classification, and c, video captioning tasks. Generally, the structure contains multimode computational blocks for diffractive propagation, including 1-dimensional tensor core, 2-dimensional tensor chain, 3-dimensional tensor array, and 4-dimensional tensor cluster. Each basic block performs near-core modulation with recurrent flows and tensor connections, which are configured with flexible input and output parameters.

Supplementary information

Supplementary Information

Supplementary Notes 1–20, Supplementary Figs. 1–17 and Supplementary Tables 1–4.

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Wang, C., Cheng, Y., Xu, Z. et al. Diffractive tensorized unit for million-TOPS general-purpose computing. Nat. Photon. 19, 1078–1087 (2025). https://doi.org/10.1038/s41566-025-01749-3

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