High gain non-isolated step-up DC-DC converter proper for renewable energy applications

Abstract

This paper introduces a quadratic-based DC-DC converter with high voltage gain, specifically optimized for DC microgrid applications. The proposed topology offers several key merits, including enhanced voltage gain, reduced voltage stress on switching components, continuous input current, a common ground between the input and output, high efficiency, and synchronized switch operation. A detailed analysis is provided on its operational principles, steady-state characteristics, design considerations, and efficiency evaluation, along with dynamic modeling and control assessment. To emphasize its benefits, the proposed converter is compared with existing topologies. The effectiveness of the design is validated through experimental testing on a 200W prototype, operating with an input voltage of 20V and delivering an output voltage of 200V.

Introduction

With the increasing integration of distributed generation sources, DC microgrid technology continues to advance. Since DC power generators typically produce low output voltages, high efficiency and high-gain DC-DC converters are essential to meet the voltage requirements of DC loads [1]. In addition to their crucial role in renewable energy systems, these high-gain converters are widely employed in various applications, including battery backup solutions for uninterruptible power supplies, high-intensity discharge lamp ballasts for automotive headlamps, electric traction systems, and certain medical devices [2].

Traditionally, conventional DC-DC boost converters have been utilized for voltage step-up applications. However, one major drawback is that the voltage stress on the switching device is equivalent to the output voltage. As a result, high-voltage-rated switches must be chosen, leading to increased conduction losses. Furthermore, achieving a high voltage gain requires operating at large duty cycles, which not only amplifies conduction losses and voltage spikes but also intensifies the diode reverse recovery issue, potentially affecting overall system performance [3].

Various advanced DC-DC circuit topologies have been developed to achieve high voltage gain by converting low-voltage sources into elevated DC output voltages. These designs incorporate multiple voltage-boosting techniques, such as switched inductor and switched capacitor (SC) methods, cascading structures, interleaved configurations, voltage multiplier cells, and hybrid approaches that integrate these methods [4,5,6,7,8,9,10,11]. While these strategies effectively enhance voltage gain, many suffer from inherent drawbacks, including the use of multiple components and hard-switching operations, which compromise their efficiency and suitability for high-gain applications.

To overcome these challenges, multi-stage or multi-level strategies have been introduced, generally categorized into three main sections: cascading, interleaving, and multilevel configurations. Despite their potential to improve voltage gain, these converters often encounter issues such as complex control requirements, an increased number of components, and higher system costs. Interleaved structures, as proposed in [12] and [13], have gained attention for photovoltaic applications due to their capability to reduce input current ripple, making them particularly beneficial in such scenarios. However, their practical implementation is prevented, by the intricacy of the control mechanism and elevated costs.

Among various voltage-boosting techniques, the SC approach, which operates on the charge pump principle, is a commonly employed method for achieving high voltage gain, as demonstrated in [14,15,16]. Nevertheless, SC-based topologies present a significant limitation: they generate high peak currents through capacitors, which can result in substantial power losses and increased electromagnetic interference. Despite this drawback, the voltage multiplier technique has emerged as a more cost-effective and efficient solution. Comprising diodes and capacitors, voltage multiplier circuits enable significant voltage gain while maintaining a relatively simple structure [17,18,19]. However, although studies in [20] and [21] highlight the capability of voltage multipliers to achieve high voltage levels, their dependence on a large number of components escalates both cost and system size. Furthermore, a major limitation of voltage multiplier circuits is the excessive voltage stress imposed on the circuit components.

Another widely implemented method for increasing input voltage and achieving high voltage gain in DC-DC converters is the voltage lift technique [22,23,24]. This approach relies on charging a capacitor to a predefined voltage level before utilizing the stored charge to elevate the output voltage. By continuously applying this principle and incorporating additional capacitors, higher voltage levels can be attained through extended configurations such as re-lift, triple-lift, and quadruple-lift techniques.

The switched inductor technique operates using two distinct configurations: the passive switched-inductor unit (PSL) and the active switched-inductor unit (ASL). In ASL-based designs, the circuit comprises active switches and inductors, whereas PSL units utilize diodes in combination with inductors [25, 26]. The ASL approach significantly enhances the voltage boost capability by first charging the inductors in parallel through two power switches. When the switches are turned off, the stored energy is then released in series, effectively increasing the output voltage, as outlined in [27, 28].

Motivated by the advantages and limitations of existing high step-up converters, this paper introduces an innovative DC-DC topology tailored for DC microgrid applications. The proposed design offers several key benefits, enhancing performance and efficiency in high step-up voltage conversion. Main contributions and features of this paper are classified as follows:

• The proposed topology, enables high voltage gain without being limited by the duty cycle, allowing it to operate across the full range from 0 to 1

• Imposing low voltage stress on the switches, allowing the use of low-voltage-rated switches with minimal on-resistance. This reduction in resistance decreases conduction losses and improves overall efficiency.

• Providing a continuous input current with minimal ripple

• Utilizing two power switches operating in synchronization.

• The input and output sides share a common ground.

The rest sections of this work are titled as follows:

Section "Proposed Step up DC-DC Converter" includes theoretical study to reach converter’s boosting gain, dynamic study and compassion study. In Sect. 3 experimental results are studied in detail. Section 4 includes work conclusion.

Proposed step up DC-DC converter

Figure 1 illustrates the basic structure of the proposed boost converter. The proposed converter includes: two switches (S₁, S₂), three inductors (L₁, L₂, L₃), three diodes (D₁, D₂, D₃) and capacitors (C₁, C₂, C₃, Co). This converter operates in two modes, continues and discontinues conduction mode (CCM, DCM). Some assumption is considered to have a comprehensive study, as follows:

• Equivalent series resistance (ESR) of all semiconductors are ignored.

• Voltage of all capacitors is considered in the constant value (due to its large magnitude)

• The transient intervals are not considered in the operational modes, because of its shorter time than switching period of time.

Fig. 1

Proposed converter.

Both of CCM and DCM operation modes are described in the following sections.

Analysis of CCM mode

CCM operation mode of the proposed converter consists of two-time intervals. S₁ and S₂ are turned on in the same time, or S₁ and S₂ are turned off in the same time. The idealized waveform of the proposed non-isolated boost converter is depicted in the Fig. 2.

Fig. 2

Voltage and current waveform of L₁ ~ L₃ and D₁ ~ D₃.

First operation mode

In this time interval, S₁ and S₂ are turned on. This time interval endures (1-D) T. D₁ and D₃ are off and D₂ is on. The blocking voltage of D₁and D₃ are, VC₁ andV_C3-V_o, respectively. Inductors L₁, L₂ and L₃ are in the charging position. Figure 3 shows the converter’s condition in this time interval. Inductors voltages are obtained via Eqs. (1–4):

$$- V_{in} + V_{L1} = 0$$

(1)

$$- V_{C2} - V_{L2} + V_{C1} = 0$$

(2)

$$- V_{C1} + V_{L3} = 0$$

(3)

$$V_{C3} = V_{C2}$$

(4)

Fig. 3

Proposed converter in the first switching interval.

Second operation mode

Figure 4 illustrates the proposed boost converter’s elements condition in the second time interval. In this mode, S₁ is in on state and S₂ is in off state. D₁ and D₂ are blocked via voltage V_C1 and V_C2-V_O, respectively. Diode D₃ is in forward bias. Inductors L₁, L₂ and L₃ are in charge, charge and discharge position, respectively. Equations (4–6) gives voltage of the inductors:

$$- V_{C1} + V_{L3} - V_{C3} + V_{O} = 0$$

(5)

$$- V_{in} + V_{L1} + V_{C1} = 0$$

(6)

$$V_{L2} + V_{C2} = 0$$

(7)

$$V_{C1} = \frac{{V_{in} }}{1 - D}$$

(8)

$$V_{C2} = V_{C3} = \frac{{DV_{in} }}{1 - D}$$

(9)

Fig. 4

Proposed converter in the second switching interval.

Volt–second law

Average voltage of inductors in the period of time is equal to zero [29]. By employing volt-second law, capacitors voltage is obtained as follows:

$$\int\limits_{0}^{T} {V_{L1} (t)dt = \int\limits_{0}^{DT} {V_{in} } } dt + \int\limits_{DT}^{T} {(V_{in} - V_{C1} )dt} = 0$$

(10)

$$V_{C1} = \frac{{V_{in} }}{1 - D}$$

(11)

$$\int\limits_{0}^{T} {V_{L2} (t)dt = \int\limits_{0}^{DT} {(V_{C1} - V_{C2} )dt} } + \int\limits_{DT}^{T} { - V_{C2} dt} = 0$$

(12)

$$V_{C2} = \frac{D}{(1 - D)}V_{in}$$

(13)

$$\int\limits_{0}^{T} {V_{L3} (t)dt = \int\limits_{0}^{DT} {(V_{C1} + V_{C3} - V_{O} )dt + } } \int\limits_{DT}^{T} {V_{C1} dt} = 0$$

(14)

$$V_{C3} = \frac{D}{(1 - D)}V_{in}$$

(15)

By using capacitor voltages, the voltage gain has been calculated as follows:

$$M_{CCM} = \left( {\frac{{V_{O} }}{{V_{in} }}} \right) = \left( {\frac{{2 - D^{2} }}{{(1 - D)^{2} }}} \right)$$

(16)

The blocking voltage of diodes and switches could be calculated as follows:

$$V_{S1} = \frac{{V_{in} }}{1 - D}$$

(17)

$$V_{S2} = \frac{{V_{in} }}{{(1 - D)^{2} }}$$

(18)

$$V_{D1} = \frac{{V_{in} }}{1 - D}$$

(19)

$$V_{D2} = \frac{{DV_{in} }}{{(1 - D)^{2} }}$$

(20)

$$V_{D3} = \frac{{V_{in} }}{{(1 - D)^{2} }}$$

(21)

Analyze of DCM mode

DCM Condition.

The first two DCM operating modes exhibit similar behavior; therefore, this section focuses exclusively on Mode II of DCM. In this mode, all switches and diodes are turned off, and the corresponding relationship derived using Kirchhoff’s Voltage Law (KVL) is as follows:

$$- V_{in} + V_{L1} - V_{C2} - V_{L2} + V_{C1} = 0$$

(22)

Utilizing the volt-second balance principle on the input inductors, accompanied by several derivations, enables the determination of the voltages across capacitors C1, C2, C3, as well as the output voltage.

$$V_{C1} = \frac{{V_{in} (D + D^{\prime})}}{{D^{\prime}}}$$

(23)

$$V_{C2} = \frac{{DV_{in} }}{{D^{\prime}}}$$

(24)

$$V_{C3} = \frac{{DV_{in} }}{{D^{\prime}}}$$

(25)

$$V_{O} = \frac{{V_{in} (D - D^{2} + 1 + D^{\prime})}}{{D^{\prime}}}$$

(26)

$$G_{DCM} = \frac{{V_{O} }}{{V_{in} }} = \frac{{(D - D^{2} + 1 + D^{\prime})}}{{D^{\prime}}}$$

(27)

Additionally, through the application of the charge balance principle to the capacitors, followed by a sequence of derivations, it becomes possible to calculate the current flowing through the inductors.

$$I_{L1} = \frac{{I_{O} (1 + D - D^{2} )}}{{D^{\prime}}}$$

(28)

Assuming IL1 = IL1(peak) /2, then IL1(peak) can be obtained, as follows:

$$I_{L1(peak)} = \frac{{2V_{O} (1 + D - D^{2} )}}{{D^{\prime}R_{O} }}$$

(29)

Furthermore, the following equation can be formulated for the inductor, as below:

$$\Delta i_{L1} = \frac{{V_{L1} \Delta t}}{{L_{1} }} = \frac{{V_{in} D}}{{L_{1} f_{s} }}$$

(30)

Time duration of the mode III can be calculated as:

$$D^{\prime} = \frac{{4\tau G_{DCM} }}{D}$$

(31)

where, τ is a dimensionless variable, and it is defined, as follows:

$$\tau = \frac{{f_{s} L_{eq} }}{{R_{O} }}$$

(32)

Boundary conduction mode (BCM)

A. Boundary condition

To ensure CCM operation in the proposed circuit, the minimum current through the L₁ must remain above zero. The minimum current of the L₁ and $\Delta I_{L1}$ can be determined as:

$$\left\{ \begin{gathered} V_{L1} = V_{in} ,\frac{{L_{1} dI_{L1} }}{dt} = V_{in} \Rightarrow dI_{L1} = \frac{{V_{in} dt}}{{L_{1} }} \hfill \\ dt = DT_{S} ,T_{S} = \frac{1}{{f_{S} }},\Delta I_{L1} = dI_{L1} ,\Delta I_{L1} = \frac{{V_{in} D}}{{L_{1} f_{S} }} \hfill \\ \end{gathered} \right.$$

(33)

$$\left\{ \begin{gathered} I_{L1,\min } = I_{L1} - \frac{{\Delta I_{L1} }}{2} \hfill \\ I_{L1,\max } = I_{L1} + \frac{{\Delta I_{L1} }}{2} \hfill \\ \end{gathered} \right.$$

(34)

The minimum required values of the L₁ to maintain CCM, as illustrated in Fig. 5, are as given.

$$\left\{ \begin{gathered} I_{L1,\min } = 0 \Rightarrow I_{L1} \ge \frac{{\Delta I_{L1} }}{2} \hfill \\ \Rightarrow \frac{{I_{O} (1 + D - D^{2} )}}{{(1 - D)^{2} }} \ge \frac{{V_{in} D}}{{2L_{1} f_{S} }} \hfill \\ L_{1} \ge \frac{{D(1 - D)^{4} R}}{{2f_{S} (1 + D - D^{2} )^{2} }} \hfill \\ \end{gathered} \right.$$

(35)

Fig. 5

The minimum needed values of the L1 for CCM function.

Current calculation

Mode I: During this time interval, Kirchhoff’s Current Law (KCL) govern the relationships in the circuit.

$$I_{L1} + I_{C2} - I_{S1} = 0$$

(36)

$$I_{L2} + I_{C1} + I_{L3} = 0$$

(37)

$$I_{L2} - I_{C2} - I_{D2} = 0$$

(38)

$$I_{D2} - I_{C3} = 0$$

(39)

$$I_{L3} + I_{C3} - I_{S2} = 0$$

(40)

$$I_{CO} + I_{O} = 0$$

(41)

$$I_{S2} + I_{C1} + I_{S1} - I_{in} = 0$$

(42)

Mode II: Using KCL, the corresponding equations for this mode can be derived as:

$$I_{L1} - I_{D1} + I_{C2} = 0$$

(43)

$$I_{D1} - I_{C1} - I_{L2} - I_{L3} = 0$$

(44)

$$I_{L2} - I_{C2} = 0$$

(45)

$$I_{D3} + I_{C3} = 0$$

(46)

$$I_{L3} + I_{C3} = 0$$

(47)

$$I_{D3} - I_{CO} - I_{O} = 0$$

(48)

$$I_{CO} + I_{O} + I_{D1} - I_{L2} - I_{L3} - I_{in} = 0$$

(49)

Current stress of the components

The currents through the semiconductor components during the first and second switching subintervals can be expressed as follows:

$$I_{S1 - Mode1} = \frac{{I_{O} (2D^{2} - 4D + 1)}}{{(1 - D)^{2} D}}$$

(50)

$$I_{S2 - Mode1} = \frac{{I_{O} }}{(1 - D)D}$$

(51)

$$I_{D1 - Mode2} = \frac{{I_{O} (2 - D)}}{{(1 - D)^{2} }}$$

(52)

$$I_{D2 - Mode1} = \frac{{I_{O} }}{D}$$

(53)

$$I_{D3 - Mode2} = \frac{{I_{O} }}{1 - D}$$

(54)

Additionally, the currents flowing through the capacitors during the first and second switching subintervals can be expressed as:

$$I_{C1 - Mode1} = - \frac{{I_{O} (2 - D)}}{(1 - D)}$$

(55)

$$I_{C1 - Mode2} = \frac{{DI_{O} (2 - D)}}{{(1 - D)^{2} }}$$

(56)

$$I_{C2 - Mode1} = - \frac{{I_{O} (1 - D)}}{D}$$

(57)

$$I_{C2 - Mode2} = I_{O}$$

(58)

$$I_{C3 - Mode1} = \frac{{I_{O} }}{D}$$

(59)

$$I_{C3 - Mode2} = - \frac{{I_{O} }}{1 - D}$$

(60)

$$I_{CO - Mode1} = - I_{O}$$

(61)

$$I_{CO - Mode2} = \frac{{DI_{O} }}{1 - D}$$

(62)

Assuming ripple-free currents for inductors during CCM operation, the average currents can be calculated as shown below:

$$I_{L1} = I_{in} = \frac{{I_{O} (1 + D - D^{2} )}}{{(1 - D)^{2} }}$$

(63)

$$I_{L2} = I_{O}$$

(64)

$$I_{L3} = \frac{{I_{O} }}{1 - D}$$

(65)

Additionally, the average currents for the converter’s switches and diodes can be approximated as follows:

$$I_{S1,avg} = \frac{{I_{O} (2D^{2} - 4D + 1)}}{{(1 - D)^{2} }}$$

(66)

$$I_{S2,avg} = \frac{{I_{O} }}{(1 - D)}$$

(67)

$$I_{D1,avg} = \frac{{I_{O} (2 - D)}}{(1 - D)}$$

(68)

$$I_{D2,avg} = I_{D3,avg} = I_{O}$$

(69)

Calculating the root-mean-square (RMS) currents is essential for assessing the overall power efficiency of the power converter. Hence, the RMS currents for each component are determined as:

$$I_{S1,rms} = \frac{{I_{O} (2D^{2} - 4D + 1)}}{{(1 - D)^{2} \sqrt D }}$$

(70)

$$I_{S2,rms} = \frac{{I_{O} }}{(1 - D)\sqrt D }$$

(71)

$$I_{D1,rms} = \frac{{I_{O} (2 - D)}}{{\sqrt {(1 - D)^{3} } }}$$

(72)

$$I_{D2,rms} = \frac{{I_{O} }}{\sqrt D }$$

(73)

$$I_{D3,rms} = \frac{{I_{O} }}{{\sqrt {1 - D} }}$$

(74)

$$I_{C1,rms} = - \frac{{I_{O} (2 - D)\sqrt D }}{(1 - D)} + \frac{{DI_{O} (2 - D)}}{{\sqrt {(1 - D)^{3} } }}$$

(75)

$$I_{C2,rms} = - \frac{{I_{O} (1 - D)}}{\sqrt D } + I_{O} \sqrt {1 - D}$$

(76)

$$I_{C3,rms} = \frac{{I_{O} }}{\sqrt D } - \frac{{I_{O} }}{{\sqrt {1 - D} }}$$

(77)

$$I_{CO,rms} = - I_{O} \sqrt D + \frac{{DI_{O} }}{{\sqrt {1 - D} }}$$

(78)

Design and efficiency

Design approach

The high-performance design is resulted by considering all of voltage and current constraints [30,31,32]. To this aim, inductance and capacitor values are calculated by considering current and voltage ripple equations as follows:

$$L_{1} = L_{2} = L_{3} \ge \frac{{D \times V_{i}^{2} }}{{0.1 \times P_{o} \times f}} = \frac{{0.6 \times 20^{2} }}{{0.1 \times 200 \times 50 \times 10^{3} }} = 24(\mu H)$$

(79)

$$C \ge \frac{{D \times V_{o} }}{\Delta V \times R \times f} = \frac{0.6 \times 240}{{4 \times 100 \times 50 \times 10^{3} }} = 7.2(\mu F)$$

(80)

Calculating efficiency of the proposed converter

The real form of proposed converter with considering parasitic resistance of elements is used to calculate its efficiency [33, 34]. R_DS-ON, R _{(D1, D2, D3)}, R _{(L1, L2, L3)}, R _{(C1, C2, C3)} are resistance of power switch, ESR of diodes, ESR of inductors, and ESR of capacitors, respectively.

$$Power_{Loss} = Loss_{Switches} + Loss_{Diodes} + Loss_{Capacitors} + Loss_{inductors}$$

(81)

$$Loss_{switches} = Loss_{Conducting} + Loss_{Switching} = R_{DS\_on} (I_{G}^{rms} )^{2} + \frac{1}{2}f_{s} (t_{r} + t_{f} )I_{G}^{ave} V_{G}$$

(82)

$$Loss_{Diodes} = \sum\limits_{i = 1}^{Num.\,diodes} {\left( {Loss_{Conduction} + Loss_{Forward} } \right)} = \sum\limits_{i = 1}^{Num.\,diodes} {\left[ {r_{{D_{i} }} \left( {I_{{D_{i} }}^{RMS} } \right)^{2} + V_{{D_{i} }} I_{{D_{i} }}^{avg} } \right]}$$

(83)

$$Loss_{Capacitors} = \sum\limits_{i = 1}^{Num.\,capacitors} {\left[ {r_{{C_{i} }} \left( {I_{{C_{i} }}^{RMS} } \right)^{2} } \right]}$$

(84)

$$Loss_{inductors} = \sum\limits_{i = 1}^{Num - inductors} {[r_{Li} (I_{Li}^{RMS} )^{2} ]}$$

(85)

$$I_{G1}^{rms} = \sqrt {2\left( {\frac{{2 - D^{2} }}{{(1 - D)^{2} }}} \right)} I_{O}$$

(86)

$$I_{G2}^{rms} = \sqrt {2(\frac{{1 - D^{2} + D}}{1 - D})} \,I_{O}$$

(87)

By implementing Eqs. (81–87) numerical power loss values of each component are calculated as follows:

$$Loss_{L1} = 0.01 \times 2.08^{2} = 0.43\,w$$

(88)

$$Loss_{L2} = 0.01 \times 0.044^{2} = 0.00002w$$

(89)

$$Loss_{L3} = 0.01 \times 3 \times 0.044 = 0.0013\,w$$

(90)

$$Loss_{C1} = 0.01 \times 7.01^{2} = 0.49w$$

(91)

$$Loss_{C2} = 0.01 \times 3.45^{2} = 0.119w$$

(92)

$$Loss_{C3} = 0.01 \times 3.9^{2} = 0.16w$$

$$Loss_{D1} = (0.7 \times 0.83) + (0.02 \times 0.017) = 0.5844\,w$$

(93)

$$Loss_{D2,3} = 2 \times ((0.7 \times 0.52) + (0.02 \times 0.1102) = 0.7324w$$

(94)

$$Loss_{G1} = [0.5 \times 50000 \times (60 + 48) \times 10^{ - 9} \times 1.25 \times 60] + [0.04 \times 0.9375] = 0.24w$$

(95)

$$Loss_{G2} = [0.5 \times 50000 \times (60 + 48) \times 10^{ - 9} \times 0.6458 \times 323] + [0.04 \times 0.25] = 0.573w$$

(96)

$$Total - Loss = 2.91w$$

(97)

$$\eta \%=\frac{{P}^{out}}{{P}^{out}+{P}^{Loss}}\times 100=\frac{50}{50+2.91}\times 100=92.63\%$$

(98)

Figure 6 illustrates the portion of each component in total power loss of the proposed converter. As it could be seen clearly, Diodes total loss are more than other elements. To have a comprehensive study, change of converter’s efficiency versus output power change is depicted as Fig. 7.

Fig. 6

Power loss of each component per total power loss.

Fig. 7

The theoretical and experimental efficiency of the proposed topology in relation to the output power.

To have a calculation approximately near to the real, inductor core losses are considered in all of calculations as follows:

$$\begin{gathered} P_{core} = kf_{s}^{a} B_{m}^{b} M \hfill \\ \hfill \\ \end{gathered}$$

(99)

$$\begin{gathered} P_{core} = kf_{s}^{a} (\frac{{L_{i} I_{Li} }}{{NA_{c} }})^{b} M \hfill \\ \hfill \\ \end{gathered}$$

(100)

$$P_{core}^{L1} = 1.04w$$

(101)

$$P_{core}^{L2} = 0.0072w$$

(102)

$$P_{core}^{L3} = 0.021w$$

(103)

$$Total - Loss = 3.98w$$

(104)

$$\eta \% = \frac{{P^{out} }}{{P^{out} + P^{Loss} }} \times 100 = \frac{50}{{50 + 3.98}} \times 100 = 91.63\%$$

(105)

Comparison Study

To assess the effectiveness of the proposed high-gain DC–DC converter, an extensive benchmark study was carried out against several existing topologies. Table 1 summarizes the main attributes of the suggested design and compares them with converters reported in [15,16,17,18,19,20,21,22,23,24,25,26,27]. The comparison considers aspects such as the number of components, overall device count, voltage gain, peak stress across switches and diodes, nominal power capacity, and input current ripple. In the voltage gain expressions of converters that utilize a coupled inductor, the parameter N denotes the turns ratio between the secondary and primary windings. This factor significantly impacts voltage gain performance. By contrast, the proposed topology is transformerless and does not rely on N, thereby avoiding leakage inductance, EMI, and additional losses typically associated with coupled-inductor-based converters. Figure 8a presents the voltage gain profile of the proposed topology in relation to other boost converters. The results indicate that the proposed design delivers a substantially higher voltage gain. This characteristic is particularly advantageous, as it enables the converter to achieve the required output at relatively low duty cycles. Operating at lower duty ratios reduces conduction losses and, consequently, enhances efficiency. Figure 8b compares the maximum voltage stress on the switches. The proposed converter demonstrates lower stress levels compared to its counterparts, allowing the use of more affordable power switches. Furthermore, minimizing switch stress directly contributes to reducing power dissipation, thereby improving overall performance. Similarly, Fig. 8c examines the voltage stress imposed on diodes. The proposed design again exhibits considerably lower stress, ensuring both cost reduction and efficiency improvement by lowering conduction and switching losses. Another critical factor considered is the input current ripple. A low input ripple is vital for renewable energy systems and other sensitive applications, as it ensures stable and reliable operation. Converters in [15,16,17,18,19, 25], and [27], listed in the comparison table, exhibit relatively high ripple levels, which restricts their suitability for such applications. The results confirm that the proposed converter delivers superior efficiency in comparison to most of the existing designs, with the exception of the configurations in [19, 23], and [26], which demonstrate slightly higher performance. In conclusion, the comparative analysis demonstrates that the proposed converter outperforms conventional designs by offering higher voltage gain, reduced stress on switching devices, and lower input current ripple. These features establish it as a strong candidate for high step-up power conversion applications.

Table 1 Comparison designing features of proposed converter with others.

Fig. 8

Comparison curves. (a) comparison of voltage gain of proposed converter with others, (b) Switches stress voltage, (c) diodes blocking voltages.

Dynamic performance

In this section, average-state- space method has been used to give the transfer function. By employing Kirchhoff’s voltage and current law, the function includes: state, input and control variable are formulated as an equation of the output and state variables. All assumptions to write state-space equations are listed as follows:

• The value of input voltage source of the proposed converter is adjusted in the constant value.

• All of utilized inductors and series resistance of them are considered equal to L₁=L₂=L₃=L and r_l, respectively

• All of utilized capacitors and series resistance of them are considered equal to C₁=C₂=C₃=C and r_c

By considering these conditions, there are 6 independent state variables. Equation (79) show the state-space form of the output variables.

$$\begin{gathered} [x_{{^{.i} }}^{.} (t)] = [A][\overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\frown}$}}{x}_{i} (t)] + [B][\overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\frown}$}}{u}_{i} (t)] \hfill \\ [\overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\frown}$}}{y}_{i} (t)] = [C][\overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\frown}$}}{x}_{i} (t)] + [D][\overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\frown}$}}{u}_{i} (t)] \hfill \\ \end{gathered}$$

(106)

Equations (79) illustrates the state variables and input variables vectors.

$$\begin{gathered} [\overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\frown}$}}{x} ] = [\overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\frown}$}}{i}_{L1} \,\overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\frown}$}}{i}_{L2} \,\overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\frown}$}}{i}_{L3} \,\overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\frown}$}}{v}_{C1\,} \overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\frown}$}}{v}_{C2} \,\overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\frown}$}}{v}_{C3} ] \hfill \\ [\overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\frown}$}}{u} ] = [v_{in} ] \hfill \\ [\overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\frown}$}}{y} ] = [\overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\frown}$}}{i}_{in} \,\overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\frown}$}}{v}_{o} ] \hfill \\ \end{gathered}$$

(107)

Steady state equations in intervals $(0\le t\le \left(D\right)T)$ which both of S₁ and S₂ are on, are written as follows:

$$\left(\begin{array}{c}{i^{\prime}}_{l1}\\ {i^{\prime}}_{l2}\\ {i^{\prime}}_{l3}\\ {v^{\prime}}_{c1}\\ {v^{\prime}}_{c2}\\ {v^{\prime}}_{c3}\end{array}\right)=\left[\begin{array}{cccccc}-\frac{{r}_{l}}{{l}_{1}}& 0& 0& 0& 0& 0\\ 0& -\frac{{r}_{l}}{{l}_{2}}& \frac{{r}_{c}}{{l}_{2}}& \frac{1}{{l}_{2}}& -\frac{1}{{l}_{2}}& 0\\ 0& \frac{{r}_{c}}{{l}_{3}}& \frac{{r}_{c}}{{l}_{3}}& \frac{1}{{l}_{3}}& 0& 0\\ 0& -\frac{1}{c1}& -\frac{1}{c1}& 0& 0& 0\\ 0& \frac{1}{c2}& 0& 0& 0& 0\\ 0& 0& 0& 0& 0& 0\end{array}\right]\times \left(\begin{array}{c}{i}_{l1}\\ {i}_{l2}\\ {i}_{l3}\\ {v}_{c1}\\ {v}_{c2}\\ {v}_{c3}\end{array}\right)+\left(\begin{array}{c}\frac{1}{l}\\ 0\\ 0\\ 0\\ 0\\ 0\end{array}\right){v}_{in}$$

(108)

The mentioned equations in interval $(DT\le t\le T)$ which G₂ is on, is written as follows:

$$\left(\begin{array}{c}{i^{\prime}}_{l1}\\ {i^{\prime}}_{l2}\\ {i^{\prime}}_{l3}\\ {v^{\prime}}_{c1}\\ {v^{\prime}}_{c2}\\ {v^{\prime}}_{c3}\end{array}\right)=\left[\begin{array}{cccccc}-\frac{{r}_{l}+{r}_{c}}{{l}_{1}}& 0& \frac{2{r}_{c}}{l1}& \frac{-1}{l1}& 0& 0\\ 0& -\frac{{r}_{l}+{r}_{c}}{{l}_{2}}& \frac{{r}_{c}}{{l}_{2}}& 0& -\frac{1}{{l}_{2}}& 0\\ \frac{{r}_{c}}{l3}& 0& -\frac{2{r}_{c}+{r}_{l}}{{l}_{3}}& \frac{1}{{l}_{3}}& 0& 0\\ \frac{1}{c1}& 0& -\frac{2}{c1}& 0& 0& 0\\ 0& \frac{1}{c2}& -\frac{1}{c2}& 0& 0& 0\\ 0& 0& \frac{1}{c3}& 0& 0& 0\end{array}\right]\times \left(\begin{array}{c}{i}_{l1}\\ {i}_{l2}\\ {i}_{l3}\\ {v}_{c1}\\ {v}_{c2}\\ {v}_{c3}\end{array}\right)+\left(\begin{array}{c}\frac{1}{l}\\ 0\\ 0\\ 0\\ 0\\ 0\end{array}\right){v}_{in}$$

(109)

by considering Eq. (84), transfer function of the proposed converter is achieved as;

$$H\left(s\right)=\frac{{V}_{o}(s)}{{V}_{in}(s)}=\frac{328{s}^{5}+8.7E8{s}^{4}+2E11{s}^{3}+4.18E17{s}^{2}+2.6E19s+1E25}{{s}^{6}+93.3{s}^{5}+1.03E9{s}^{4}+8E10{s}^{3}+2.3E17{s}^{2}+1.4E19s+1.5E24}$$

(110)

Figure 9 illustrates the phase and gain margin of Eq. (84).

Fig. 9

Phase and gain margin of proposed converter transfer function.

To make a stability discussion, close-loop model and diagram are figured as Fig. 10.

Fig. 10

Close loop block diagram.

To improve stability of close-loop model, by PID controller is used. Pole placement technique is used to equivalent model poles. To adjust PID controller, Ziegler and Nichols, tuning technique is used as follows [29]:

$$C\left(s\right)=Kp\times (1+\frac{1}{{T}_{i}S}+{T}_{d}s)$$

(111)

where: ${T}_{i}=4\times {T}_{d}$

To improve phase margin with utilizing PID controller, the new transfer function is achieved as follows:

$$H\left(s\right)=\frac{{V}_{o}\left(s\right)}{{V}_{in}\left(s\right)}=\frac{51{s}^{5}+8.7E4{s}^{4}+48E6{s}^{2}+23.4E7s+1E12}{{s}^{6}+83.6{s}^{5}+1.03E3{s}^{4}+8E4{s}^{3}+1.4E19s+2.8E24}$$

(112)

Figure 11 illustrates the bode diagram of close loop model with adjusted PID controller.

Fig. 11

Closed-loop bode diagram.

Experimental results

To validate the theoretical analysis and demonstrate the practical applicability of the proposed high-gain converter, a 200 W experimental prototype was developed. The key design specifications are provided in Table 2. Figure 12 presents the gating signals applied to switches S₁ and S₂. The measured inductor currents, displayed in Fig. 13a–c, closely follow the values derived from Eqs. (63–65), confirming the accuracy of the analytical model. Experimental results also verify the current and voltage stresses on the diodes. As shown in Fig. 14a, diode D₁ conducts 13 A at 37 V. Diode D₂ sustains 38 V and 9 A [Fig. 14b], while D₃ operates at 38 V and 5 A [Fig. 14c]. Capacitor voltages are consistent with theoretical predictions as well: Fig. 15 records 37 V across C₁ compared to the calculated 40 V from Eq. (11), and around 19 V across C₂ and C₃, which is close to the expected values from Eqs. (13) and (15). The prototype also delivers an output voltage of 195 V with a current of 1 A, as indicated in Fig. 16. These values are in strong agreement with the predicted 200 V from Eq. (16). Switching device stresses were further examined: Fig. 17a shows that S₁ is subjected to a maximum of 36 V and 10 A, while Fig. 17b indicates that S₂ withstands 75 V and 14 A. Both sets of measurements are consistent with the calculated results. In summary, the strong correlation between the analytical expectations and the experimental observations across Figs. 13–17 confirms the correctness of the theoretical analysis and validates the high performance of the proposed converter.

Table 2 Experimental data of laboratory prototype.

Fig. 12

switching pattern of G₁ and G_2.

Fig. 13

Experimental Results. (a) current waveform of L₁, (b) current waveform of L₂, (c) current waveform of L₃.

Fig. 14

Experimental Results for diodes, (a) Voltage and current waveform of D₁, (b) Voltage and current waveform of D₂, (c) Voltage and current waveform of D₃.

Fig. 15

Capacitor’s voltages.

Fig. 16

Output voltage and current.

Fig. 17

Experimental Results for the power switches. (a) voltage and current of switch S₁, (b) voltage and current of switch S₂.

The proposed converter was tested under various load conditions and input values. In Fig. 18a, the output voltage of the converter initially registers around 96 V with a power output of about 200 W. When the load is suddenly altered and the output power is adjusted to 300 W, the output voltage remains relatively stable after brief transient fluctuations. The output voltage deviates only slightly from the reference value, demonstrating the stability of the closed-loop system in maintaining the output voltage close to the target. Figure 18b depicts the output voltage response when the input voltage suddenly drops from 20 to 15 V. It is evident from Fig. 18b that the output voltage shows minimal variation in response to the input change. Figure 19 illustrates the prototype of the proposed step-up converter.

Fig. 18

Dynamic response of the proposed converter, (a) step change of the load, (b) step change of the input voltage.

Fig. 19

Experimental model.

Conclusion

This paper introduces a quadratic high step-up topology designed to minimize input current ripple, specifically tailored for DC microgrid applications. Low-power and low-voltage implementations of this topology typically support output ranges from a few watts to several tens of watts, with voltage levels spanning from 12 to 100V. The proposed converter is particularly well-suited for powering small-scale systems, including sensors, communication devices, and low-power appliances such as LED lighting. Additionally, it plays a major role in regulating the output of residential fuel cells (typically between 24 and 100V) to align with the operating voltage requirements of the microgrid. The suggested topology provides several notable advantages, such as increased voltage gains, lower voltage stress on switching components, continuous input current, a shared ground between the input and output, high efficiency, and synchronized switch operation. The adaptability of this topology makes it ideal for a wide range of applications, including robotics and switch-mode power supplies. In industrial environments, it effectively regulates DC motor speeds in assembly lines by controlling the DC link voltage.