The artificial intelligence (AI) era has catalyzed a paradigm shift from standalone devices in personal computer (PCs) and smartphones to human-centric hyper-connected environments, including smart homes and autonomous vehicles. This transformation generates vast amounts of data, driving continued growth and innovation within the semiconductor industry while creating an unprecedented demand for high-speed, high-density, energy-efficient, and cost-effective devices. Historically, the industry has adapted to this demand by scaling up silicon (Si) wafer sizes—from 100 mm in the 1970s to 300 mm in the 2000s—and through continuous advancements in the miniaturization of Si-based devices1.

However, as technology nodes approach sub-3 nm dimensions, intrinsic limitations of silicon channels in logic transistors pose substantial challenges to further device scaling2,3. Rather than focusing solely on miniaturization, the industry is shifting towards three-dimensional (3D) device stacking. This strategy that leverages both the 2D surface area and 3D volumetric space of wafers to achieve higher integration density while minimizing device size. Despite the potential of this approach, unexpected issues related to 3D integration persist, underscoring the need for innovative architecture-designs and component-materials to overcome these limitations and enable compact, efficient, and stable 3D device architectures (Fig. 1).

Fig. 1: Development history and future direction of semiconductor device technology: material, device and integration.
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This figure outlines the progression of semiconductor technology, categorized into three main areas: materials, devices, and integration strategies. The Angstrom era highlights advancements in channel materials (2D materials), interconnects (topological semimetals), and gate stacks (ferroelectric materials) as devices approach sub-1 nm nodes. On the device side, innovations such as 2DM-MBC and CFET logic, along with vertical channel structures for DRAM and NAND, exemplify the move towards 3D architectures. Integration methodologies like DTCO and STCO, including advanced packaging and back-side power delivery, are essential to realizing compact, high-performance 3D architectures5,17,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98.

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Two-dimensional materials (2DMs), defined by their angstrom-scale thickness, stable surface properties, unique electronic structures, and superior thermal properties, are promising candidates for advanced logic transistors at sub-1 nm technology nodes, referred to as the angstrom era4. These materials offer high carrier mobility, mitigate short-channel effects, and support gate length scaling—key requirements for next-generation devices3,5,6,7,8,9,10,11,12. The thin-channel body structure also facilitates a reduction in standard cell height (z-direction), which not only reduces power consumption but also supports higher device density through multiple-tier stacking. Over the past decade, significant advances have been made in the large-area growth of 2DMs13, reduction of contact resistance14, control of equivalent oxide thickness (EOT)15, and reduction of middle-of-line (MOL) parasitic capacitance16. Despite these achievements, the semiconductor industry has historically been conservative in adopting new materials, especially in the intricate architectures of logic transistors.

However, very encouragingly, the 2022 International Roadmap for Devices and Systems (IRDS)—a strategic guide by leading semiconductor manufacturers—acknowledges the need for 2DM integration in 3D devices, particularly at the 0.7 nm technology node (2034 year), marking the dawn of the “Angstrom Era” (Fig. 1 left)17. This pivotal moment calls for a decisive advancement in the design and integration of sophisticated 3D device architectures. Specifically, the development of 3D stacking channels, such as 2DM-based multi-bridge-channel (2DM-MBC) and 3D stacking (3DS) devices, complementary field-effect transistor (CFET, aka 3DS-FET) architectures18, as well as interconnect innovations grounded in Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO), is essential to overcoming current barriers and driving transformative progress in semiconductor technology19,20 (Fig. 1 right). However, significant progress is still needed, as effective control over 3D device architectures remains an unresolved challenge.

This review article provides a critical and comprehensive examination of integration strategies for 2DMs in advancing 3D logic-integrated architectures, with a specific focus on CFETs. It begins by discussing design directions and key considerations for CFET structures (Session I, Fig. 2). Following this, it explores Si-based MBC CFET processes (Session II, Fig. 3) and examines current advancements, challenges, and innovation pathways for integrating 2DM-based MBC CFET structures (Session III, Fig. 4). Finally, it addresses the performance requirements for industrialization, focusing on the challenges of scaling up for reliable and robust industrial applications (Session IV, Fig. 5). By synthesizing the current state of research and development in 2DMs and 3D integration technologies, this review aims to provide a detailed roadmap for future advancements in the field. It highlights the importance of continued innovation and collaboration between academia and industry to overcome existing barriers and realize the full potential of next-generation semiconductor devices.

Fig. 2: Integration process of Si-MBC FETs and transition challenges for 2DM-MBC FETs.
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The left panel illustrates the requirements of conventional integration process for Si-based MBC FETs, which includes four main steps: (i) large-area and high-quality epitaxial growth of Si/SiGe stacks, (ii) selective etching to create stable, free-standing Si channels, (iii) formation of a high-quality gate structure surrounding the channel, and (iv) low-resistance source/drain contacts and doping compatible with CMOS. The right panel highlights the specific challenges of adapting this process for 2DM-based MBC FETs and proposes potential solutions. Key challenges in adapting Si process to 2DMs are highlighted: (i) achieving wafer-scale, single crystalline epitaxial growth of 2DMs at low temperature, (ii) maintaining stable free-standing and damage-free 2DM channels during the release process, (iii) depositing high-k dielectrics on 2DM surfaces and controlling interfacial stability, and (iv) developing CMOS-compatible doping and low contact resistance techniques for 2DMs. The right panel outlines potential solutions to these challenges.

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Fig. 3: Structural Overview of 2DM-MBC CFETs and Key Design Considerations for Optimal Performance.
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The diagram is divided into three main factors in 3D device architecture: (i) stacking order, (ii) integration scheme, and (iii) interconnect configuration. Each section represents critical parameters to enhance electrical performance, layout efficiency, process simplification, cost efficiency, and reliability.

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Fig. 4: Integration challenges of sequential and monolithic CFET architectures.
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Technical challenges are addressed in device performance, thermal management, process integration, and manufacturing complexity for both architectures. The top panel depicts the challenges associated with sequential CFETs, including (i) high process costs, (ii) limited thermal budget, (iii) wafer bonding defects, (iv) misalignment between top-tier and bottom-tier devices, and (v) wide isolation between P and N devices. The lower panel shows the challenges of monolithic CFETs, which include (i) limited design flexibility, (ii) difficulty in separating threshold voltages for P and N transistors, (iii) high aspect ratio structures, (iv) challenges in ensuring electrical isolation between P and N devices, and (v) increased contact resistance in bottom devices.

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Fig. 5: Reliability considerations for process integration and device operation of 2DM-MBC CFETs.
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Key challenges in integration process include (i) adhesion and bonding, (ii) recess etching, (iii) contact formation, and (iv) interconnect and power management. Critical considerations for device operation include (v) thermal management and (vi) dielectric reliability.

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Integration process of Si-MBC FETs and challenges in transitioning to 2DM-MBC FETs

The gate-all-around (GAA) architecture in FETs provides significant advantages in electrical performance, including enhanced gate control, reduced leakage current, lower operating voltage for improved power efficiency, and minimized short-channel effects (SCE)21 Furthermore, the MBC structure, compared to conventional GAA, provides a relatively wider effective channel width, resulting in higher saturation current and superior scalability, making it highly suitable for high-performance applications22. These advantages make the MBC configuration a foundational element for the CFET architecture. However, several key challenges remain in the MBC integration process when using 2DMs, which is why recent implementations of CFETs with 2DMs have primarily focused on 2D planar FETs rather than 2D-MBC FETs5,10,11,12. This session, as illustrated in Fig. 2, outlines the key requirements for integrating 2DMs into the MBC FET structure and proposes potential solutions and future directions to overcome these challenges while accommodating the unique properties of 2DMs.

  1. (i)

    Large-area, high-quality 2DMs epitaxial growth: In Si-MBC FETs, the epitaxial growth of Si/SiGe stacks is a well-established and reliable process that consistently produces defect-free layers over large areas. However, achieving large-area, high-quality growth of 2DM channels, such as MoS2 and WSe2, remains challenging due to their sensitivity to processing conditions, including temperature, humidity, and pressure. Current chemical vapor deposition (CVD) techniques often result in small grain sizes and numerous defects, which negatively impact device performance. To address these challenges, alternative low-temperature methods, such as plasma-enhanced atomic layer deposition (PE-ALD) and molecular beam epitaxy (MBE), are being investigated to facilitate the wafer-scale growth of high-quality, single-crystalline 2DMs with uniform properties and minimal defects12,23.

  2. (ii)

    Stable free-standing structure formation of 2DM channels: In Si-MBC FET integration, Si channels are released by selectively etching a sacrificial SiGe layer, a relatively straightforward process owing to the mechanical robustness of silicon. However, forming stable, free-standing 2DM channels is far more challenging due to their atomically thin nature. For instance, during the channel release process, the selective etching of dummy gate materials or sacrificial layers can cause considerable damage to 2DM channels. To address this issue, low-power plasma etching techniques are being developed to minimize damage, and post-etch healing processes are employed to restore the crystalline structure of 2DM channels, thereby enhancing their mechanical and electrical properties24,25,26. Additionally, alternative approaches, such as dry etching and critical-point drying, are being explored to reduce capillary forces and ensure the stability of free-standing 2DM channels27.

  3. (iii)

    Formation of high-quality gate structure surrounding the channel: Constructing a defect-free, four-sided gate structure around 2DM channels is challenging due to their atomic-scale thickness and extreme sensitivity to surface defects and contamination. Consequently, many studies focused on 2DM-MBC FETs struggle to demonstrate optimal device performance9,28. To address these challenges, high-k dielectrics such as Al2O3 and HfO2 can be deposited using ALD or MBE in ultrahigh vacuum (UHV) environments to achieve defect-free interfaces on the dangling-bond-free surfaces of 2DMs7,18,29,30. Techniques such as plasma surface activation, contamination removal, and post-deposition annealing are critical for maintaining interface stability and preventing contamination. Furthermore, the development of high-k dielectric 2DMs could further stabilize the interface with 2DM channels, ensuring long-term device reliability31,32.

  4. (iv)

    CMOS-compatible low contact resistance and doping: In Si MBCFETs, traditional doping techniques, such as ion implantation, are commonly used to control the electrical properties of the channel and minimize contact resistance. However, these approaches are unsuitable for 2DMs, as they can cause significant damage to the atomically thin 2D layers. Therefore, the development of damage-free doping methods for 2DMs is crucial for achieving low contact resistance and high device performance. Substitutional doping techniques, such as Nb-doped MoS2 and V-doped WSe2, have demonstrated potential in modulating the electrical properties of 2DMs without causing substantial damage33,34. Additionally, gate stack-induced permanent channel doping offers precise control over doping levels while preserving the structural integrity of the 2DM channel35,36,37. Reducing contact resistance between 2DMs and metal electrodes remains another critical challenge. This issue can be alleviated by incorporating semi-metals like Bi and Sb, doping the contact region of 2DM channels, or exploring naturally P-type materials such as Te and TeO2 to enhance PMOS performance38,39,40,41,42,43,44.

Design directions and key considerations for CFET structures

Building on the foundational advances of 2DM-MBC FETs, CFETs are gaining attention for their potential to offer significant improvements in Performance, Power, Area, and Cost (PPAC). CFETs represent a next-generation architecture that addresses many of the limitations of conventional transistor designs by stacking PMOS and NMOS devices in a three-dimensional configuration. This architectural innovation provides promising pathways for continued scaling beyond the limits of traditional planar transistors. As shown in Fig. 3, to achieve optimal outcomes in CFET structures, three main key factors in 3D device architecture must be carefully considered: (i) the stacking order of P-Channel Metal-Oxide-Semiconductor (PMOS) and N-Channel Metal-Oxide-Semiconductor (NMOS); (ii) stacking integration, including sequential versus monolithic; and (iii) the interconnect configuration, particularly the power delivery network (PDN)23,24,25,26,27.

  1. (i)

    Stacking order: In CFETs, the MBC structure is utilized in both NMOS and PMOS structures to improve device performance, as discussed in Session I. The stacking order plays a critical role in determining overall performance and process compatibility, influenced by the characteristics and thermal requirements of each layer. The bottom layer is designed to accommodate high-temperature processes, providing a higher thermal budget and enabling a simplified layout. In contrast, the top layer is constrained by lower process temperatures and stricter layout considerations to prevent degradation of the bottom layer’s performance or stability. For instance, deposition, annealing, and implantation processes for the top layer must achieve equivalent performance metrics, such as mobility and on-current, under mild processing conditions to match the bottom channel23,24. Thus, the P/NMOS ordering is crucial for optimizing CFET performance, ensuring CMOS equivalence, and maintaining compatibility with advanced integration processes.

  2. (ii)

    Integration Scheme: CFETs can be integrated using either sequential or monolithic stacking, each offering distinct advantages. Sequential CFETs involve bonding two separate wafers, one containing NMOS and the other containing PMOS FETs. This approach provides flexibility in material selection and integration environments. The larger separation between channel dielectrics results in higher breakdown voltage and lower leakage current. However, the wafer bonding process increases device height and effective interconnect pitch, leading to higher parasitic capacitance and resistance, which in turn elevate power consumption and induce signal delay. Additionally, sequential integration is highly sensitive to misalignment and limited by the thermal budget. In contrast, monolithic CFETs are directly integrated on a single wafer by aligning top- and bottom-tier devices, making them cost-effective and suitable for height scaling5,10,25. This configuration reduces parasitic capacitance and resistance, enabling higher effective current generation, i.e., lower power consumption. However, it introduces design complexity and poses reliability challenges due to the narrow dielectric isolation between P/NMOS channels. Further integration challenges associated with sequential and monolithic 3D FETs will be explored in Session III.

  3. (iii)

    Interconnect Configuration: While interconnection layers constantly increase (more than 13 layers in back-end-of-line (BEOL)) to connect already scaled-down FETs, the interconnect configuration becomes more serious in 3D device architecture. The back-side power delivery network (BSPDN) offers a promising solution by positioning logic circuits on the front side and power supply or signal routing on the back side, thereby improving power efficiency over conventional interconnects. This arrangement enables broader and more direct pathways, minimizing the resistance and capacitance of metal interconnects and avoiding the complexity of the BEOL stack. This improvement enhances efficiency for front-end routing, signal integrity, and timing accuracy. Overall, BSPDN alleviates routing congestion and supports further reductions in standard cell height, which is crucial for 3D architectures, where stacking increases the vertical interconnect pitch and facilitates semiconductor chip miniaturization26,27. Requirements for 2DM-MBC CFET reliability, including interconnect configurations, will be further discussed in Session IV.

Integration challenges of sequential and monolithic CFETs

CFETs introduce a set of unique challenges that must be addressed to realize their advantages fully. This session discusses the key integration difficulties associated with the two primary CFET architectures: sequential CFETs and monolithic CFETs. Each architecture presents distinct technical challenges in terms of device performance, thermal management, process integration, and manufacturing complexity, as summarized in Fig. 4 and Table 1.

Table 1 Integration challenges of sequential and monolithic CFET
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Challenges in sequential CFETs

Sequential CFETs involve fabricating the bottom-tier device first, followed by wafer bonding with a top-tier wafer that contains only the pre-formed channel. The top-tier device is then integrated sequentially through chemical-mechanical polishing (CMP) and BEOL processes. This approach offers greater flexibility in material selection and processing, as each device layer can be independently optimized before integration. However, this flexibility also introduces several critical challenges:

  1. (i)

    High process cost: The use of two wafers, along with bonding and CMP steps, significantly increases manufacturing costs. Additionally, the increased wafer thickness extends interconnect length, further complicating integration and raising fabrication expenses. Process simplification and cost-reduction strategies are essential for enabling commercial scalability45,46.

  2. (ii)

    Limited thermal budget: Fabrication of the top-tier device requires a series of advanced lithography steps and low-temperature processing to prevent degradation of the bottom-tier device47,48. Issues such as dopant diffusion and gate dielectric instability can degrade carrier transport properties49,50. While plasma-assisted deposition and other low-temperature techniques help mitigate these risks, they introduce further process complexity.

  3. (iii)

    Wafer bonding defects: Wafer bonding integrates top-tier devices on bottom-tier wafers but can cause mechanical stress, leading to warping, bending, or breakage, which affects yield and reliability. Additionally, contaminants or defects at the bonding interface can also impact performance. Advanced bonding techniques with improved defect control are crucial for overcoming these issues.

  4. (iv)

    (iv) Misalignment: Precise alignment between the top-tier and bottom-tier devices is critical in sequential CFETs to avoid performance degradation51. Misalignment can increase parasitic resistance and capacitance, negatively impacting device speed and power consumption. The requirement for advanced lithography tools, such as extreme ultraviolet (EUV), to achieve this precision further adds to the cost and complexity of manufacturing.

  5. (v)

    (v) Wide P/N isolation: Sequential CFETs require wide isolation between the PMOS and NMOS devices to prevent crosstalk and ensure proper operation. However, this wide isolation increases thermal resistance and parasitic capacitance or resistance, which can degrade overall device performance45,52. Moreover, the increased area required for isolation reduces the density of devices, which is counterproductive to scaling goals46.

Challenges in monolithic CFETs

Monolithic CFETs integrate both top- and bottom-tier devices on a single wafer, forming the channels first, followed by source/drain and gate formation, inter-tier middle-of-line (MOL) connections, and BEOL processing. This compact approach eliminates wafer bonding and minimizes alignment errors but introduces its own challenges:

  1. (i)

    Limited design flexibility: Monolithic CFETs require simultaneous fabrication of PMOS and NMOS devices, restricting their independent optimization46,53. Finding materials and processes that meet the distinct requirements of both device types is a significant challenge. This lack of flexibility complicates process integration and limits performance optimization.

  2. (ii)

    Multi Vth for P/N devices: Achieving separate threshold voltages (Vth) for the PMOS and NMOS devices is critical for optimal switching behavior54,55,56. However, the shared processing environment complicates doping and gate stack engineering, leading to increased leakage and power consumption. Advanced doping techniques are needed to ensure precise Vth control.

  3. (iii)

    High aspect ratio: The tall and narrow structures required for monolithic CFETs create challenges in etching, deposition, and patterning. Simultaneous gate fabrication for both tiers necessitate high aspect ratio processing, making these structures prone to non-uniformity and mechanical instability, increasing defect risks. Additionally, the increased complexity of these structures can result in longer production times and higher manufacturing costs.

  4. (iv)

    P/N electrical isolation: Ensuring effective electrical and thermal isolation between the PMOS and NMOS devices is critical in monolithic CFETs to prevent leakage currents and thermal interference57,58. Poor isolation can lead to increased crosstalk, elevated leakage, and reduced device reliability. Advanced insulators and optimized isolation techniques are essential for maintaining electrical and thermal separation, thereby overcoming this challenge.

  5. (v)

    Large middle-of-line RC: The bottom-tier devices in Monolithic CFETs experience increased contact resistance due to limited contact area and mechanical stress from the top-tier devices59,60,61. This increased resistance degrades the performance of the bottom-tier devices, leading to higher power dissipation and heat generation. Solutions such as utilizing semi-metals or advanced contact engineering are necessary to minimize RC and enhance the overall reliability and performance of Monolithic CFETs.

Currently, Si-based sequential CFETs are an ongoing process development. The implementation of sequential and monolithic CFETs using 2DM-MBC has more hurdles. However, to achieve the ultimate goal of compact 2DM-MBC-based monolithic CFETs, it is crucial not only to refine fabrication processes innovatively but also to creatively advance materials, such as 2D channels, metals, and low-k dielectrics, that retain stability under aggressive scaling conditions.

Promising integration strategies for enhancing the reliability of 2DM-MBC CFETs

This section examines key factors that must be addressed to ensure the reliability of both the integration process and device operation of 2DM-MBC CFETs, thereby facilitating the transition from laboratory innovations to high-volume manufacturing.

  1. (i)

    Adhesion and Bonding: Adhesion properties crucial for achieving high fabrication yields and device reliability, particularly during high-temperature processing or under mechanical strain. Specifically, the inert nature of 2DM surfaces affects interfacial adhesion with surrounding materials, which impacts integration efficiency and electrical performance. For instance, a robust adhesion between the channel and gate stacks is essential to maintaining device integrity. In monolithic 2DM-MBC CFETs, differences in adhesion energy between top- and bottom-tier channels arise from material selection, processing steps, polarity control, and deposition conditions. When a common gate controls both PMOS and NMOS devices, these variations can induce mechanical stress, compromising reliability. In sequential 2DM-MBC CFETs, precise control of adhesion energy is necessary for bonding techniques such as flip-chip or hybrid Cu-Cu bonding to ensure high yield and uniformity during top- and bottom-tier integration5,6. Optimized interface engineering and process refinement are critical to achieving reliable and scalable 2DM-MBC CFETs integration.

  2. (ii)

    Recess Etching: The recess etching process, which is crucial for creating a free-standing 2DM channel, poses challenges, as it may damage the channel material. High-selectivity sacrificial layers are thus vital for ensuring clean etch profiles and preventing damage6. Since the free-standing channels formed through recess etching are susceptible to capillary forces during solution-based processes, it is critical to develop etching techniques that minimize such damage. Current research on etching for 2DM focuses on achieving layer-by-layer etching without damage. The KOH etching can be utilized in the recess channel process, demonstrating high etching selectivity for the WOx/WSe2 channel and realizing damage-free channels62. To form a free-standing 2DM channel that enables conformal contact, techniques that enable all-sided etching of channels are required, employing a sacrificial layer with high etch selectivity.

  3. (iii)

    Contact Formation: The formation of low-resistance contact between the 2DM channel and the metal electrode remains challenging63,64,65. While high doping locally to contact regions is often used to reduce contact resistance, the situation is more complex for 2DMs due to their sensitivity to process-induced crystal defects. Conformal contacts, which form electrical connections on the top, bottom, and edges of the channel, effectively reduce the contact length while increasing the overall contact area. This enables a smaller contacted poly pitch (CPP) while minimizing contact resistance, a critical requirement for efficient 3D integration6. While edge contacts have received considerable attention14,66,67, further research into conformal contact approaches, incorporating factors such as CMOS-compatible metal deposition and high thermal budget, is needed to fully optimize contact resistance4,63,64,65.

  4. (iv)

    Interconnect: The BSPDN, which places the power delivery network on the wafer’s backside, plays a crucial role in interconnect design by reducing voltage drop, enhancing power efficiency, minimizing footprint, and improving overall performance65. Key technologies such as buried power rail (BPR), which embeds power rails within the Si substrate, and nano through-silicon vias (nano-TSVs) through silicon enable sub-micron interconnect pitch68,69. However, BSPDN integration for 2DM-MBC FETs is still in its early stages, and significant technical challenges are expected for its integration into 2DM-MBC CFETs16.

  5. (v)

    Thermal Management: A densely packed 3D architecture like MBC CFET requires effective thermal management, as increased power density can create localized hotspots, degrading performance and reliability70. Thermal transport in 2DMs has been extensively studied for thermal management in the 3D integration of 2DM FETs65,71. Heat dissipation strategies include device structure engineering, such as backside power delivery (BPR) engineering to reduce thermal resistance and enhance drive current, and material property engineering, which mitigates self-heating through defect control72, heterostructures73, doping74, and strain75. Further research into in-plane and out-of-plane heat transport across contacts, interconnects, vias, and dielectric isolation is essential for optimizing thermal management in 2DM-MBC CFETs.

  6. (vi)

    Dielectric Reliability: Ensuring device reliability is critical for the qualification of 2DM-MBC CFETs, particularly in addressing defects and charge trapping in the dielectric. Process integration must minimize dangling bonds in the 3D dielectric oxides and strain-induced defects in the gate stacks, which can lead to charge trapping at interfaces and border traps. However, these factors are often overlooked in academic studies. Key reliability tests include hysteresis and bias temperature instability (BTI) monitored by Vth shift, hot carrier injection (HCI) evaluated by gate-induced drain leakage (GIDL), time-dependent dielectric breakdown (TDDB) assessed via breakdown voltage or voltage ramping (Vramp), and high-temperature operating lifetime (HTOL) testing. Selecting dielectrics optimized for 2DM channels and ensuring thorough monitoring of these reliability metrics in 3D-integrated structures are essential. Identifying optimal materials and advancing process integration within a comprehensive reliability framework must be addressed to realize the full potential of 2DM-MBC CFETs for next-generation logic transistors4,63,64,65.

Conclusion and outlook

The development of 2DM-MBC FET and CFET architectures is still in its early stages, with many challenges yet to be fully addressed. However, this paper provides a comprehensive analysis of the advantages, critical challenges, and key development strategies along with potential improvement paths that are expected to accelerate the advancement of this field. If successfully implemented, the 2DM-MBC CFET will revolutionize semiconductor technology, enabling ultra-small, high-performance, and energy-efficient devices that surpass the limitations of current silicon-based architectures. This advancement will not only enhance computing performance and efficiency but also fundamentally transform the technological landscape by opening the door to new applications in the IoT, AI, and edge computing, bringing us closer to the era of ubiquitous intelligent connectivity.