Fig. 1: Cost breakdown for packaging in microelectronics and microphotonics.

In (a), data for Samsung’s fan-out panel level packaging (FO-PLP) manufacturing of the Google Tensor G2 system-on-chip (SoC)¹¹. The data in (b) shows similar data for the manufacturing of a fiber coupled, integrated InP PIC with modulators and detectors¹². The data in (c) is for FO-WLP, but nonetheless provides information on a breakdown by process for electronic packaging cost drivers¹³. Similarly, (d) does the same breakdown by process for the InP PIC¹². Finally, (e) provides the overall cost breakdown for a ubiquitous electronic-photonic system—a SiPh transceiver⁸