Fig. 4: Structure schematic and emulation of the synaptic functions of InSe FETs. | Microsystems & Nanoengineering

Fig. 4: Structure schematic and emulation of the synaptic functions of InSe FETs.

From: Recent progress in three-terminal artificial synapses based on 2D materials: from mechanisms to applications

Fig. 4: Structure schematic and emulation of the synaptic functions of InSe FETs.

a Schematic diagram of the InSe FET exposed to ambient conditions. b Schematic illustration of a biological synapse and the InSe artificial synaptic device. c EPSC generated by applying several input spikes with different voltage amplitudes under the enhanced condition. d Plot of IPSC changes over 120 s after stimulation by various numbers of input pulses. Adapted with permission202. Copyright 2020, Springer Nature

Back to article page