Fig. 8

The complete process flow for chip fabrication. a Wafer cleaning using standard RCA procedures. b Lithographic patterning of sensitive diaphragm patterns. c Electroplating of masked Ni layer. d Deep dry etching of sensitive diaphragm back cavity. e Lithographic patterning of sensitive piezoresistors patterns. f Dry etching of sensitive piezoresistors. g PECVD of the SiO2 layer. h Lithographic patterning of ohmic contact areas. i Opening ohmic contact window. j Sputtering Ni metal layer and lift off. k Rapid thermal annealing. l Forming the metal lead layer