Fig. 3

Fabrication process of the integrated cantilever chips a KOH etching of sample-loading region after thermal oxidation. b Ion-implantation of resonant excitation and readout resistance. c LPCVD SiNx and polysilicon deposition. d Fabrication of thermocouples through ion-implantation, diffusion, and RIE, and then depositing LPCVD SiNx. e Patterning of Mo heater and Al electric connection. f PECVD film deposition for antioxidant protection. g DRIE for the device layer to pattern the shape of the cantilever. h DRIE is used to handle the layer and release the cantilever