Fig. 3: Layout, photo, impedance matching circuit, and comparison of the performance of the fabricated SAW RFID with optimized RMSCs with simulation results. | Microsystems & Nanoengineering

Fig. 3: Layout, photo, impedance matching circuit, and comparison of the performance of the fabricated SAW RFID with optimized RMSCs with simulation results.

From: Low-loss SAW RFID using the reflective multistrip coupler as reflectors

Fig. 3

a Schematic layout of the SAW RFID with RMSC reflectors. b Photo of the fabricated chip. c Schematic of impedance matching circuit for the SAW RFID. d Measured Smith chart of the unmatched and matched SAW RFIDs. e Measured frequency domain response of the unmatched and matched SAW RFIDs. f Measured time domain response of the unmatched and matched SAW RFIDs

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