Fig. 5
Large-scale device integration and scaling with graphene-based, electric-field-assisted nanomaterial placement. a Artistic rendering of a Si/SiO2 substrate with embedded metal electrode and a patterned graphene layer for field-assisted carbon nanotube placement. The scanning electron microscope (SEM) false color image reveals how the graphene layer (red) is patterned to form gaps at the position of the embedded metal electrode (yellow) for facilitating the nanotube placement. Scale bar: 1 µm. b Artistic rendering and SEM false color image of the carbon nanotube placement across the embedded metal electrode (yellow), at the substrate surface, before the graphene electrodes are removed (red). Deposition conditions are VDEP = 3 V, f = 1 MHz, t = 5 min. Scale bar: 200 nm. c Layout of large-scale integration based on the device architecture in a–f. The insets display SEM images of individual devices taken at representative locations of a mm-scale assembly structure, as well as an SEM image of a larger set of individually addressable devices. Scale bars (from left to right): 200 nm, 50 µm, and 200 nm. d Artistic rendering and SEM false color image (top view) showing final carbon nanotube array transistor, after removal of graphene layer and manufacturing of metal contacts. Scale bar: 100 nm. e Electrical transfer characteristics of a carbon nanotube array transistor. f Electrical output characteristics of a carbon nanotube array transistor
