Fig. 3

DC electrical characterization of back-gated bilayer MoS₂ transistors at room temperature and low temperatures. a Optical micrograph of back-gated MoS₂ transistors with different channel lengths. Scale bar is 10 μm. b The corresponding SEM images of the active device region and the zoom-in picture. Scale bar are 2 μm and 100 nm, respectively. c The I_ds − V_gs transfer characteristics at 50 mV bias voltage and g_m − V_gs curves at 1 V bias voltage for the 3 μm channel length back-gated monolayer (blue line and open diamonds, respectively) and bilayer (magenta line and open diamonds, respectively) MoS₂ transistors. d, e The I_ds − V_ds output characteristics of the bilayer MoS₂ transistor at 300 K and 4.3 K. The back-gate voltages vary from −1 to 3 V with a step of 0.5 V. f The extracted intrinsic field-effect mobility versus temperature of bilayer MoS₂ FETs. g The I_ds − V_gs transfer characteristics at 50 mV bias voltage at room temperatures for different channel lengths of 40 nm (magenta line), 500 nm (blue line), and 3 μm (black line). h The I_ds − V_ds output curves at 300 K and 4.3 K for bilayer MoS₂ transistors with a channel length of 40 nm. A record I_on of 1.52 mA μm⁻¹ was achieved