Fig. 1 | Nature Communications

Fig. 1

From: Van der Waals negative capacitance transistors

Fig. 1

CIPS/MoS2 vdW heterostructure and NC-FET. a, b Schematic diagram (a) and False-color SEM image (b) of a CIPS/MoS2 vdW NC-FET. Scale bar, 2 μm. c Cross-sectional high-resolution TEM image of a vertically stacked CIPS/MoS2 heterostructure on SiO2/Si substrate and corresponding EDS elemental map showing the distribution of Mo, S, Cu, In, and P. Scale bar, 5 nm. d, e PFM amplitude (d) and phase (e) of a CIPS/MoS2 vdW heterostructure. The CIPS/MoS2 stacked region is enclosed by dashed lines in (d). Scale bar, 2 μm. f The off-field PFM amplitude (top) and phase (bottom) hysteresis loops during the switching process for CIPS flake

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