Fig. 2 | Nature Communications

Fig. 2

From: Van der Waals negative capacitance transistors

Fig. 2

Room temperature electric characterization of CIPS/MoS2 vdW NC-FETs. a Schematics of the characterization configuration for back-gate measurements. b, c Back-gate Ids−Vbg characteristics (red) and leakage current (blue) (b) and SS−Ids characteristics (c) of a CIPS/MoS2 NC-FET. Vds = 0.5 V. d Schematics of the characterization configuration for top-gate measurements. e, f Top-gate Ids−Vtg characteristics (red) and leakage current (blue) (e) and SS−Ids characteristics (f) of the same device as in (b). g Ferroelectric hysteresis dependence on Vbg. Inset: SS extracted from the top-gate Ids−Vtg characteristics at various Vbg. h Top-gate transfer characteristics of vdW NC-FETs with different thickness of CIPS. V*tg = Vtg-Vth, where Vth is the threshold voltage measured with top gate. i CIPS thickness dependence of SS (top) and hysteresis width (bottom). Symbol, experimental data; Line, simulation

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