Fig. 1: Ultra-long nano-wires formation.
From: Templated dewetting of single-crystal sub-millimeter-long nanowires and on-chip silicon circuits
a Scheme of the sample fabrication: long patches are created in a 12 nm thick ultra-thin silicon on insulator (UT-SOI) on buried oxide (BOX, SiO\({}_{2}\), 25 nm) with a pitch of \({d}_{{\rm{LL}}}\) and width \(w\). b Scanning electron microscope (SEM) image of 21 parallel nano-wires of length 0.75 mm, \({d}_{{\rm{LL}}}\) = 1.3 \(\upmu\)m, and \(w\) = 700 nm (a high-resolution image with the full wire length is provided in the high-resolution Supplementary Data 1). Annealing temperature was 775 \({}^{\circ }\)C for 30′ in ultra-high vacuum (10\({}^{-10}\) Torr, circa). The yellow areas highlight the etched trenches. Bottom right inset: blow up of a free-propagating edge and a dewetted wire. The distance covered by a freely receding rim is highlighted by \(\Delta x\). c Top panel: detail of the extremity of the wires. Bottom-right panel: blow-up of a wire extremity.
