Fig. 3: Simulations of the memristor analog content-addressable memory cell.

a The layout design of one analog content-addressable memory (CAM) cell in an analog CAM array using commercial 16 nm design rules. The transistors in this proof-of-concept design are over-sized to allow large driving currents. b Simulated transient voltage response on the Match Line (ML) where the different curves show searches with different Data Line (DL) voltages for a matching case (red) and two mismatching cases (blue, green). c The circuit simulation with the same memristor configuration shown in (b) shows that the cell matches a range of DL voltage, whose bounds are independently controlled by the conductances of the two memristors in the cell. d The simulated relation between the search range and the memristor conductance. The blue curve shows the lower bound of the stored range, while magenta shows the upper bound. e, f Using differently configured memristor conductances, the cells in the array can store (e) a continuous range of values, or (f) discrete levels (showing eight levels or 3-bits).