Fig. 4: CMOS logic functions based on WSe2 transistors with different contact approaches.
From: Doping-free complementary WSe2 circuit via van der Waals metal integration
a Circuit diagram (upper) and optical image of a typical complementary inverter composed of two WSe2 transistors in series, where one is contacted with deposited Au electrodes (n-type) and another is contacted by vdW Au electrodes (p-type). Scale bar in the optical image is 4 μm. b The voltage transfer characteristics of the inverter as a function of the input voltage with different Vdd from 1.5 to 5.5 V (1-V step). c The corresponding voltage gains of the resulting inverter. d The bistable hysteresis voltage transfer characteristics of WSe2 CMOS logic inverter as a function of the input voltage (Vdd = 2.5 V), with the noise margin low (NML) of 1.16 V and noise margin high (NMH) of 1.19 V achieved. The VOH, VOL, VIL, and VIH represent the minimum high output voltage, maximum low output voltage, maximum low input voltage, and minimum high input voltage for the inverter, respectively. e The ratio of the total noise margin as a function of Vdd. f NAND and NOR circuit diagram composed of four WSe2 transistors, where two are contacted with deposited Au electrodes as n-type devices, and another two are contacted by vdW electrodes (p-type). g, h The input–output logic functions of NAND (g) and NOR (h) circuits. Gate voltage of −30 and 0 V is used as input “0” and “1”, respectively. Vds bias voltage is fixed at 0.23 V.
