Fig. 2: Observation of the native oxidation layer by microscopic structure analysis. | Nature Communications

Fig. 2: Observation of the native oxidation layer by microscopic structure analysis.

From: Oxidation-boosted charge trapping in ultra-sensitive van der Waals materials for artificial synaptic features

Fig. 2

a Cross-sectional HRTEM image and the corresponding EDS element mappings of a typical InSe A-FET. The arrows highlight the existence of the InOx layer. b EDS line scan profiles of In, O, Se, and Si elements along the cross-section region of the device. Note that the dash lines label the region of InOx. c Energy band structure of the charge trapping and releasing process of Program and Erase operations for InSe A-FET under different gate voltages (Vbg). The Program and Erase operations are defined as the charge trapping process by InOx and charge releasing process from InOx, respectively. d Schematic diagram of boosted threshold voltage variation for InSe A-FET compared with that for InSe V-FET.

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