Fig. 5: CuInSe2-CQD-based integrated CMOS NAND and NOR logic gates.
From: Solution-processable integrated CMOS circuits based on colloidal CuInSe2 quantum dots
a Processing steps used to fabricate a CMOS NAND gate based on CuInSe2 CQD PFETs and NFETs. Two separate Au gate electrodes are prepared for applying input voltages (VA and VB). b A schematic depiction (not to scale) of the fabricated CMOS NAND gate device (top) along with its photograph (bottom left) and the circuit diagram (bottom right); VDD = 5 V is the supply voltage and Vout is the output voltage. c The measured output voltage of the NAND gate for four different combinations of input signals: (VA, VB) = (0, 0), (1, 0), (0, 1), and (1, 1). d, e Same as in (b) and (c), respectively, but for the fabricated NOR logic-gate device. Scale bars in panels (b) and (d) correspond to 5 mm. Source data are provided as a Source Data file.
