Fig. 3: Cycle endurance and time retention characteristics.
From: Van der Waals engineering of ferroelectric heterostructures for long-retention memory
a Top-gate Ids−Vtg characteristics (red) and leakage current (black) of a vdW FeFET measured with Vds = 0.5 V and internal gate floating. The device has a four-layer MoS2 channel and an 86-nm-thick CIPS layer. b Dynamic characteristics of the same vdW FeFET in response to periodic top-gate voltage pulses with an amplitude of 3.5 V and width of 1 s. Ids was probed with Vds = 0.5 V after applying the gate pulse. Inset shows the periodic pulse mode applied to the top gate. c Endurance performance through more than 104 P/E cycles. d Retention properties of this device at the program and erase states. Ids was monitored at Vds = 0.5 V and Vtg = 0 V.
