Fig. 4: The photo-patternability of iRUM-s and iRUM-d, and the integrated patterned elastic transistors on a single substrate.

a Schematic illustration of the photo-patterning process for iRUM-s, which involves selective UV exposure and chloroform development. Optical microscope images of photo-patterned iRUM-s film (thickness: 35 nm) before and after depositing MoO₃/Au (2 nm/55 nm) electrodes. b A representative transfer curve of iRUM-s film that is photo-patterned on OTS-modified SiO₂ (300 nm) as characterized in a bottom-gate top-contact transistor. c Mobility distribution of photo-patterned iRUM-s from 10×10 photo-patterned transistors on a single substrate, with bottom-gate top-contact configuration, highly doped Si as gate electrode, MoO₃/Au as source/drain electrodes (W = 500 µm, L = 50 µm) and octadecyltrimethoxysilane (OTS)-modified SiO₂ (300 nm) as dielectrics. d Surface roughness characterization of SEBS and iRUM-d-4:5 films by profilometer before- and after-solvent treatment. e The mobility of photo-patterned iRUM-s film on iRUM-d-x:y (1–1.5 μm thick), where x:y is the BH-to-SEBS weight ratio. f A representative transfer curve of a bottom-gate top-contact transistor with iRUM-s directly photo-patterned on iRUM-d-4:5 (1 μm thick). g The representative stress-strain curves for SEBS and iRUM-d-4:5 films obtained from pseudo-free-standing tensile tests. h Cyclic stress-strain curves (10–70% strains) for iRUM-d-4:5. i Schematic of fully patterned, stretchable, and elastic transistors on a single substrate. Two-dimensional diagram showing the side view of the transistor structure. j Changes in mobility for the patterned elastic transistors after multiple stretching-releasing cycles at 50% strain, with charge transport parallel and perpendicular to stretching direction.