Fig. 1: A comprehensive picture of building MoS₂ 2D-FETs.

a Demonstration of uniform wafer-scale MoS₂ growth by CVD, including a schematic diagram of the material-growth equipment, a batch of 2-in. wafer-scale sapphire substrates uniformly covered with MoS₂, a 2-in. sapphire wafer uniformly covered with MoS₂ marked with Raman test points, and Raman mapping spectra from different locations marked in the previous picture. b Schematic cross section of an MoS₂ FET with TG (top gate) and global BG (bottom gate). Various interface factors that influence the device performance are categorized, including the insertion of seeding layer (SL) between MoS₂ and high-k dielectric (in this work, SL is deposited on the entire channel region), the interface between the TG and high-k dielectric, and the interface between MoS₂ and contact metals. c Schematic diagram of the relationship between performance parameters of the transistor and performance limitations of the integrated circuit, where µ, V_T, I_on/I_off, and SS represent the mobility, threshold voltage, current on/off ratio, and subthreshold swing. d Process flow and feedback-optimization diagram from material synthesis to industrial-grade circuit design, fabrication, and test.