Fig. 3: Logic circuits based on MoS2 TG-FETs. | Nature Communications

Fig. 3: Logic circuits based on MoS2 TG-FETs.

From: Wafer-scale functional circuits based on two dimensional semiconductors with fabrication optimized by machine learning

Fig. 3

Experimental data (circular dots) and simulation (lines) for a, b transfer and output characteristics of MoS2 TG-FETs, and c, d display voltage-transfer curves (VTCs) of an MoS2 inverter with M1 and M2 FETs. The inset in c is the schematic of a MoS2 pseudo-NMOS inverter. The geometry parameter R = (W/L)M1/(W/L)M2 is used to adjust the switching point of the VTC curve in c, while a different method is used in d by independently tuning VT of M1. e is an optical microscope image of a MoS2-negative edge-triggered D flip-flop (DFF) circuit, and f shows the corresponding experimental results. The upper two waveforms are inputs with a 0–3 V voltage swing, and the lower graph shows the measured output. g is an optical microscope image of a 1-bit MoS2 full adder and h is the corresponding experimental results. The output signal of sum (S) and carry output (Co) is distinguished by the shaded gray areas.

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