Fig. 5: Wafer-scale integrated circuits built from MoS2 FETs.
a Photograph of a 2-inch MoS2 wafer with 1-bit full-adder arrays as functional circuits in the center, and MoS2 TG-FET arrays used as monitoring devices locating in the surrounding regions. All MoS2 TG-FETs and 1-bit full-adders are fabricated within the red dashed square. The zoom-ins of blue dashed boxes are optical microscope images of the corresponding MoS2 TG-FET and 1-bit full-adder arrays. b Wafer maps of mobility (left) and VT statistics (center) extracted from devices in the surrounding regions. The yellow scale bars show mobility and VT values. Each block’s color scale represents a value averaged from 16 FETs, and the entire wafer has 81 blocks. The right graph illustrates the yield of 1-bit full-adder circuit arrays. The red and gray squares represent the proportion of working and nonworking circuits, respectively. c Optical microscope image of a 4-bit full adder under which is the truth table for logical combinations. d Functional measurements of the 4-bit full adder with VDD = 3 V. The 4-bit full-adder was tested using a series of input combinations (A, B) in the following order: (0000 + 0000, 0000 + 0111, 1111 + 1000, 1111 + 1111) with Ci = 0 and Ci = 1. The y axes are the voltage of carry input (Ci) and carry output (Co), and the output voltage of sum0 (S0), sum1 (S1), sum2 (S2), sum3 (S3).
