Fig. 3: Device-to-device uniformity. | Nature Communications

Fig. 3: Device-to-device uniformity.

From: Vertically stacked, low-voltage organic ternary logic circuits including nonvolatile floating-gate memory transistors

Fig. 3

a Schematic illustration of the organic flash memory on the first floor, b transfer characteristics of the 11 memory devices, and c their threshold voltage (VT), on/off current ratio (Ion/Ioff) variation. d Schematic illustration of the heterojunction transistor (HTR) on the second floor, e transfer characteristics of the 11 HTR devices, and f their negative transconductance (NTC) length, peak-to-valley current ratio (PVCR) variation. g voltage transfer characteristics (VTCs), h DC gain profiles, and i intermediate logic value, DC gain variation of the 11 3-dimensional (3D) ternary logic inverter (T-inverter) devices.

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