Fig. 4: The 3-dimensional (3D) ternary logic inverter (T-inverter) performance according to the programming state of the flash memory. | Nature Communications

Fig. 4: The 3-dimensional (3D) ternary logic inverter (T-inverter) performance according to the programming state of the flash memory.

From: Vertically stacked, low-voltage organic ternary logic circuits including nonvolatile floating-gate memory transistors

Fig. 4

a A schematic diagram of the incremental step pulse programming (ISPP) of the flash memory. b The transfer characteristics of the memory and c change in threshold voltage (VT) with respect to a programming voltage (Vprg). A schematic illustration of d the 3D T-inverter with different flash memory states and e 3D T-inverter measurement. f The voltage transfer characteristics (VTCs), g intermediate logic value, and h DC gain values according to Vprg of the flash memory.

Back to article page